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I am using PMOS as a switch to control 24V to deliver to load. When MCU drives the NMOS it is suppose to pull the PMOS gate to GND and turn-on so that load can get the 24V. This is what expected as per circuit 1.

circuit

However, PMOS has VGS max rating of 20V so circuit 1 can damage the PMOS when it is ON. so to protect the PMOS from exceeding VGS rating on internet I came across 2 methods. That I have given in image as circuit 2 and circuit 3.

Circuit 2 uses voltage divider, when the PMOS is on, to ensure VGS is just 4V (24 V - 19 V) and stays within limit.

Circuit 3 uses zener of 15V to clamp voltage to 15V across VGS.

Just unable to understand if circuit 2 works then why would anyone go with circuit 3 and additional zener on board.

Thanks in advance.

Regards,

BRT

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  • \$\begingroup\$ Circuit 2 is a bit slow, the FET is in linear range for some time until it is fully conducting. This may be a thermal issue. If the supply voltage does not reach the 24 V this may be the reason for another thermal problem. \$\endgroup\$
    – Jens
    Jun 14, 2023 at 15:49

1 Answer 1

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The on-state VGS is negative for PMOS, so use -4V, -15V, etc instead of 4V, 15V. Although we understand what you mean, it's always good to know and use the correct way.


Circuit 2 uses voltage divider, when PMOS on to ensure VGS is just 4V

Just unable to understand if circuit 2 works then why would anyone go with circuit 3 and additional zener on board.

RDS-on value, the on resistance of the MOSFET, gets lower and lower as the gate-source voltage approaches to the absolute max (or min?) value, which is -20V in your case. So, instead of trying to keep it around the threshold, such as -4V as in circuit 2, try to keep it between the threshold and the max value, preferably close to max (e.g. -15V). This will give you possibly minimum on-resistance without exceeding the limits of the device.

It's also good to use a Zener across the gate-source – the input voltage varies (e.g. between 16V and 40V) the risk of exceeding the absolute limits of the device decreases, or you can design the divider for possible minimum and maximum input voltage.

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  • \$\begingroup\$ Hi, Thanks for taking time and answering. Yes I should have used negative voltage while refereeing VGS of PMOS. I understood that even though circuit 2 works it can not protect against wide variable input voltage range(24V - 90V). \$\endgroup\$
    – Brt
    Jun 15, 2023 at 14:36

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