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My power electronic device has either of these infeed waveforms connected in 3-phase:

  1. Inverter (+/-325V to +/-720V 16kHz PWM square wave to produce 0-200Hz sine)
  2. Standard mains (50/60Hz, 130-540VAC RMS)

I intend to detect positive and negative phase-to-phase edges from (1) and report them to my FPGA with low latency, because responding to the PWM step changes is a control challenge. The aim is to detect edges for pulses of >320V magnitude with <4us edge.

I have designed a circuit as below. I would be using Toshiba TLP2367 optocouplers, but I couldn't get a LTSpice model for them, so I simulated with 6N137s.

optoisolated edge detection circuit

C1 & R1 produce a current pulse for sufficiently steep waveforms. R2 allows for a faster discharge of C1 to keep the pulses sufficiently short while not over-driving the opto.

OptopPos/OptoNeg: opto output voltage. Ix(U1:A)/Ix(U2:A): Current into LED anode.

result of simulation, 16kHz +/-325V waveform with 4us slopes

As far as I can see:

  • C1 (several in series?) needs to be rated to 720V+safety margin.
  • R1 (several in series?) needs to be rated to 1440V+safety margin. As worst-case, V1 will flip from +720 to -720 while C1 is positively charged. Rated for power dissipation according to a crisp +/-720V squarewave.
  • All need to be selected to ensure the maximum current through the opto is not exceeded.

It seems like it will work, but I may be naïve to some practical considerations. Have I missed anything?

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  • \$\begingroup\$ What happens when the duty cycle is minimum? \$\endgroup\$
    – Andy aka
    Commented Jun 18, 2023 at 7:44
  • \$\begingroup\$ @Andyaka good point and that is why I wanted to run it by you guys. Assuming 0.1% PWM minimum, that's 62.5ns which I think can make its way to the FPGA without being filtered out. The FPGA can detect <10ns width pulses. \$\endgroup\$ Commented Jun 18, 2023 at 8:30
  • \$\begingroup\$ @Andyaka and now I get your question. What would happen is a screw up. @ 0.1% PWM (62.5ns), the FPGA can detect the pulses and their time order, but to discharge in time for the negative edge detection, C1 would need a silly value (4.7p). So I'd say in order to have a designable capacitance (100p+?) I'd be looking at detecting min. 0.5% duty. \$\endgroup\$ Commented Jun 18, 2023 at 8:52
  • \$\begingroup\$ I was actually thinking that very thin pulse widths would never get through the opto-isolators and, I have no idea what Ix(U1:A) is all about relative to your schematic. Opto anode current? You need to look at the opto outputs. \$\endgroup\$
    – Andy aka
    Commented Jun 18, 2023 at 9:16
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    \$\begingroup\$ Consider that the standard mains also can contain some high voltage burst artefacts. \$\endgroup\$
    – Jens
    Commented Jun 19, 2023 at 0:41

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