I am trying to simulate the step response of an inverting integrator and a non-inverting integrator.

However, in the inverting integrator's output (blue plot), I see an initial overshoot in the opposite direction after which the output ramps towards the -ve Vee.

What is the reason for this “pre-shoot”?

The same phenomenon is not seen in the case of a non-inverting integrator (blue plot).

Also, the initial output of the inverting integrator is at +Vsat whereas for the non-inverting integrator, it is 0. Why is this?

The LTspice schematic and results are attached here. I have used the OP-AMP THS4211 from TI.

Schematic and results

EDIT 1: I have disabled the initial point calculation, and revised the picture again.

Revised schematic and results

  • \$\begingroup\$ Initial operation points are not very reliable with no DC feedback path. It is prudent to either force it with the .ic command or to disable the initial operation point calculation. \$\endgroup\$
    – tobalt
    Commented Jun 19, 2023 at 11:55
  • \$\begingroup\$ I have edited the picture after running with the .uic command. \$\endgroup\$ Commented Jun 19, 2023 at 12:07
  • \$\begingroup\$ May I ask you a slightly awkward question: "Do you understand what the ideas of the two circuits are? Are they perfect, and if so, why?" \$\endgroup\$ Commented Jun 20, 2023 at 10:05

1 Answer 1


The loop has a finite bandwidth due to which, once a step input is applied, it will take time for the inp to become equal to inn terminal.

In the case of the inverting amplifier, when the input step occurs, it will lead to a spike in the inn voltage (until the loop reacts to bring it back to 0V) and hence the spike will be seen in the output voltage as well through coupling via the feedback cap.

In the case of the non-inverting amplifier, when the input step occurs, it will lead to a step in the inp voltage (with a slower rise time as determined by R5-C3 combination) but there is no cap to couple it to the output.

  • \$\begingroup\$ Yes, I agree that there will be a low pass filtering when the step reaches inp terminal which will increase the rise time but it is still a jump in the voltage seen on inp terminal. I will update my answer. \$\endgroup\$
    – sai
    Commented Jun 19, 2023 at 12:01
  • \$\begingroup\$ Thanks very much. This answers the issue. \$\endgroup\$ Commented Jun 19, 2023 at 12:06
  • \$\begingroup\$ You could accept the answer if you like. This link gives more details electronics.stackexchange.com/help/someone-answers \$\endgroup\$
    – sai
    Commented Jun 20, 2023 at 5:39

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