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I've been diligently working on designing a variable load for the purpose of testing both AC and DC power supplies. For this task, I have opted for the integration of back-to-back MOSFETs in the circuit design.

The gate driver I've selected for this task is the UCC21520, based on the datasheet provided by the manufacturer. After thoroughly studying the datasheet and meticulously connecting the circuit as per the provided guidelines, I endeavored to simulate the circuit using PSpice for TI.

Unfortunately, the simulation didn't provide the expected results. The issue that I am currently struggling with is the constant voltage of approximately 10 V I observe at the gate of M2. This deviates from my original intent, which was to activate and deactivate both MOSFETs with a delay of 130 ns, hence varying the load through modulation of the PWM signal's duty cycle.

Despite my best efforts, I find myself unable to locate the source of this anomaly. Thus, I am reaching out to this knowledgeable community in search of help.

I would be immensely grateful for any assistance or insights you could provide in this matter. If there is anything in my methodology that you think might be leading me astray, or if there are any suggestions for improving the circuit design or simulation process, I am eager to hear your thoughts.

The circuit I assembled as per the UCC21520 datasheet guidelines

The simulation results, illustrating the around constant 10V at the gate of M2

The datasheet excerpt from where I derived my circuit design

How I calcualted some values

How I calcualted some values

How I calculated some values

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  • \$\begingroup\$ M2 looks to be upside-down. \$\endgroup\$
    – Ste Kulov
    Jun 19 at 21:10
  • \$\begingroup\$ Yes, it is upside down, I wanted to connect the sources of the MOSFETs to make it back-to-back configured. So the load can support both AC and DC power supplies.Please let me know if I did any mistakes in the configuration. \$\endgroup\$
    – Cinar Reis
    Jun 19 at 21:21
  • \$\begingroup\$ You must start from a much more basic stage. By what mechanism is your load supposed to operate? You show two transistors shorted across what is presumably a mains power source. This will destroy itself in a few hundred nanoseconds, depending on when during the line cycle it is plugged in. Begin with a problem statement (adjustable analog load? voltage drop / current source / resistance?). Begin enumerating circuits that implement that. Test them for all expected V, I conditions. Preferably, breadboard it too. Then build a complete SCH and PCB. \$\endgroup\$
    – Tim Williams
    Jun 19 at 22:40
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    \$\begingroup\$ "The duty cycle of the PWM signal is adjusted to control the effective resistance of the MOSFETs" -- you will need to justify this claim. What is "the UPS"? \$\endgroup\$
    – Tim Williams
    Jun 19 at 23:17
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    \$\begingroup\$ Yes you said that. But you didn't establish how "PWM signal" "adjusts effective resistance". Most likely you will charge up loop inductance during the on-pulse, and discharge it into the transistors (avalanche breakdown) during the off-pulse. Destruction follows shortly. The source does not see an ohmic load, it sees a hellacious torrent of radio-frequency energy. What is your proposed method to resolve these issues? \$\endgroup\$
    – Tim Williams
    Jun 20 at 0:03

1 Answer 1

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From this appnote:

enter image description here

To make an AC switch with two MOSFETs, only one driver is required. Both FETs have their sources tied together, so the driver (shown as a battery on the schematic) applies a positive Vgs to both. It's a bit counter-intuitive for the bottom FET because it's upside down, but it also gets a positive Vgs just like the top one.

In the off state, both FETs have their body diodes reversed, so they block AC. In the on state, both FETs are on, so the switch resistance is 2xRdsON.

he duty cycle of the PWM signal is adjusted to control the effective resistance of the MOSFETs, thus varying the load on the UPS. I'm aware of the potential for short-circuiting, and I'm trying to to prevent it with implementing dead time in the PWM signals

This won't work: since you used two drivers (one per FET) the driver either turns the FET on or off. If one of the FETs is on but not the other, the one that's off will simply act as a diode. In this state, we have the low RdsON of the FET that is turned on in series with a diode from the FET that's off, so the switch will pass current only in one direction but it won't limit current.

If this load is intended to test a power supply... most power supplies have capacitors on the output so this will make huge current spikes and destroy the MOSFETs.

In addition to drive this arrangement you need a floating isolated supply which is referenced to the FETs' sources.

Now I wanted to make a pure sine wave dimmer for my water heater to make it use only the power produced by my photovoltaic installation without drawing from the grid, and that's pretty much the same thing as what you want to do, so here's the result:

enter image description here

There's a mains voltage rectifier and filter to avoid injecting HF current into mains, then a simple asynchronous buck converter driving a resistor. I went with a buck because the resistor is quite large and has some inductance, so using PWM on it directly would cause spikes and high electromagnetic field emissions. Whereas feeding it a filtered voltage from the output of a buck produces much less emissions.

So the rectified input voltage is chopped according to the PWM duty cycle, then fed to the load resistor. From the point of view of the AC IN source, the result is a load that looks like the resistor divided by PWM duty cycle with a good power factor and clean sine wave input current.

It is possible to put the diode on the negative side and the MOSFET on top, but then the driver supply needs to be floating. This can also be done by replacing the diode with another MOSFET to make the buck converter synchronous. This makes it more complicated, without much reward. The low side driven FET is simple, and using a SiC diode for D5 cuts down on diode recovery loss on FET turn-on.

This hasn't been built or tested, so caveat.

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  • \$\begingroup\$ Thank you for your insights. I understand your point about using a single driver for both MOSFETs. However, I'm considering an H-bridge configuration with two isolated gate drivers for better control over current flow and load. I'm struggling with the gate driver configuration in this setup, particularly to prevent shoot-through and ensure efficient operation. Could you provide some guidance or resources on configuring gate drivers in an H-bridge setup? Your help would be greatly appreciated.(what is wrong with the above gate driver cofirugation) \$\endgroup\$
    – Cinar Reis
    Jun 20 at 21:28
  • \$\begingroup\$ What exactly do you want to do with the H-bridge for this application? It's not clear how it would help. Answer to "What's wrong with the driver in the question": with the back to back MOSFETs as AC switch, gate drive voltage is referenced to the sources which are tied together, and this voltage is floating relative to ground. So you would need a floating isolated power supply, but there isn't one. \$\endgroup\$
    – bobflux
    Jun 20 at 22:13

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