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For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either:

  • 2 TX differential pairs (of different lanes)
  • 2 RX differential pairs (of different lanes)
  • one TX differential pair and one RX differential pair (from same or different lane)
  • one TX or RX pair with respect to the clock differential pair?

NB: I'm not speaking about intra-pair skew (i.e. between the positive and negative track of a given differential pair), for which the constraints are quite tight (0.12 mm max of length difference)

So far, the data I found hints that there is no constraint (ex: this guideline section 2.5: "Max Inter-Pair Skew: No Inter-pair specification"). So is there any constraint/recommendation/advice on inter pair skew? Or can I do whatever I want (while respecting max length for each differential pair) without any impact on the result?

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    \$\begingroup\$ The whole point of using multiple lanes is the relative independence of the timing between them. There will be an upper limit where the receiving software notices that all the data hasn't arrived, but that need only be frame-length(s) sort of time, not bit-times, so not a skew spec. One would hope that this limit is defined somewhere for each application. \$\endgroup\$
    – Neil_UK
    Commented Jun 20, 2023 at 15:56
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    \$\begingroup\$ IIRC, it works out as such a large value that nobody bothers to specify it - something like 1-2 metres difference between different pairs can be compensated for. \$\endgroup\$ Commented Jun 20, 2023 at 15:58
  • \$\begingroup\$ So in practice, on a 8*15cm PCB, I can route each pair "as I want" without taking into account the inter-pair length difference. Correct? \$\endgroup\$
    – Sandro
    Commented Jun 20, 2023 at 16:01
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    \$\begingroup\$ @Sandro that's correct, yes. I'll see if I can look up the definitive reference again and post an answer if I can find it. But from experience I've never shown any concert about length matching PCIe inter-pair, with a few cm difference never having caused an issue. \$\endgroup\$ Commented Jun 20, 2023 at 16:28

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According to the PCIe base specification (Rev 3.0), Table 4-24, the following lane-to-lane (inter pair) skews are tolerable for different lane rates:

Parameter 2.5 GT/s 5.0 GT/s 8.0 GT/s Unit
Lane to Lane Skew 20 8 6 ns

For reference on a PCB microstrip, the trace speed is usually on the order of 60-70% speed of light, so 1 metre is approximately 5 nanoseconds of skew. For Gen 1-3, skews of more than a metre are permissible.

Granted this doesn't cover PCIe Gen 4, but in principal it should be a similar order of magnitude, probably around 4 ns of skew. Even if we go conservative and say 1 ns, that's still 20cm difference between different pairs in the same link.

The numbers are basically so large that it would be impractical to violate them, which is likely why the skew parameter is rarely specified.

This skew parameter applies to lanes within a link. Different links can have arbitrary skews as each link is entirely independent. Tx and Rx lanes can also have arbitrary skews as data flow in each direction is independent.

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