I am currently designing a PNP-based linear regulator (see images). However, I am having trouble with it oscillating.
There is a sizable 200 mV saw wave oscillation at its output. No, it's not power supply ripple, as it is a 16 kHz waveform.
I've done some reading and based on what I have read tried to add a capacitor (labeled as Cstab on schematic) between the Op-Amp output and it's non-inverting input. Eventually I found that putting the capacitor between the INVERTING input and the output solves the problem and that at no load/full 1A load - 100 nF is the minimum value for this capacitor.
My main question is:
How do I calculate what minimum capacitor do I have to use to stop the oscillations, and why does it have to be between the inverting input and Op-Amp output, rather than the non-inverting input and Op Amp output? - when that is my feedback path?
My Op-Amp is setup in a strange way as I'm using it to drive PNP transistors, meaning that when Vout is lower than Vset (desired regulator output voltage) it has to sink current (lower its output voltage), and if the output voltage is higher than the set voltage it must source current (increase its output voltage) to turn off the transistors.
Two values have been changed between the calculations as seen on photo 2 and what I ended up using for my prototype:
- Rp is 10 K not 2.3 M
- Cstab is 100 nF and between the INVERTING input of the Op-Amp and its output. (Connected directly, without any other components in between).
List of values for all components:
- RL: 2k
- Rset: 10K Potentiometer
- Rb: 18k
- Rp: 10k
- Rf1: 1.002k
- Rf2: 998R
- Cstab: 100nF
- Power Transistor: Toshiba 2SA1930
- Small Transistor: Sony 2SA1203
- Op Amp: JRC NJM2904
- Voltage Reference: NEC uPC1093
Additional info on how I calculated everything: