# Preventing Op Amp oscillation in PNP Linear Regulator Supply

I am currently designing a PNP-based linear regulator (see images). However, I am having trouble with it oscillating.

There is a sizable 200 mV saw wave oscillation at its output. No, it's not power supply ripple, as it is a 16 kHz waveform.

I've done some reading and based on what I have read tried to add a capacitor (labeled as Cstab on schematic) between the Op-Amp output and it's non-inverting input. Eventually I found that putting the capacitor between the INVERTING input and the output solves the problem and that at no load/full 1A load - 100 nF is the minimum value for this capacitor.

My main question is:

How do I calculate what minimum capacitor do I have to use to stop the oscillations, and why does it have to be between the inverting input and Op-Amp output, rather than the non-inverting input and Op Amp output? - when that is my feedback path?

My Op-Amp is setup in a strange way as I'm using it to drive PNP transistors, meaning that when Vout is lower than Vset (desired regulator output voltage) it has to sink current (lower its output voltage), and if the output voltage is higher than the set voltage it must source current (increase its output voltage) to turn off the transistors.

Two values have been changed between the calculations as seen on photo 2 and what I ended up using for my prototype:

• Rp is 10 K not 2.3 M
• Cstab is 100 nF and between the INVERTING input of the Op-Amp and its output. (Connected directly, without any other components in between).

List of values for all components:

• RL: 2k
• Rset: 10K Potentiometer
• Rb: 18k
• Rp: 10k
• Rf1: 1.002k
• Rf2: 998R
• Cstab: 100nF
• Power Transistor: Toshiba 2SA1930
• Small Transistor: Sony 2SA1203
• Op Amp: JRC NJM2904
• Voltage Reference: NEC uPC1093

Additional info on how I calculated everything:

• Just a note for now: stability problems include oscillation and also peaking and ringing. There are a number of well-known 'fix' approaches: dominant pole comp, lead-lag comp, lead comp, etc. But the bottom line is that many opamps you will wind up using are internally compensated and circuit capacitance (which you obviously have, given the output capacitor) can readily get oscillation and/or ringing started by supplying the phase shifts needed to become unstable. If I get a moment, I may try to say something more. (Looks like you've already accidentally discovered dominant pole comp.) Jun 20 at 22:29
• Is $C_{OUT}$ known and fixed, or is this intended to be a general purpose supply, where $C_{OUT}$ could be anything? Jun 21 at 3:52
• You have Cstab shown in the wrong place. It should go from the output of the opamp and the positive input of the opamp. If the opamp was setup for unity gain you would need a resistor between Vout and the positive input. Jun 21 at 21:17

The darlington PNP is a bit of an paradox: I guess you're using a PNP for low dropout, but the darlington has a minimum dropout voltage of 1.2V, and for this dropout voltage you could use a NPN instead, which would be much easier.

A LDO like the one above is a closed loop system which acts as controlled current source (the output is the collector of the pass transistor). On the contrary with a NPN pass transistor, the output is a voltage.

In order to make this kind of LDO stable you have to consider the whole loop, and that includes the output capacitor.

Let's say you have an error voltage which is the difference between the actual output and the desired output.

This goes to the opamp which applies its open loop gain, which is very high at DC then hits the dominant pole (usually at a low frequency like 1-100Hz) and then decreases -20dB/decade with 90° phase lag. So you have one dominant pole.

The output of the opamp is a voltage, which drives the darlington. This will have very high transconductance and add two poles at a few hundred kHz to a few MHz depending on the transistors, current, etc.

Then the output of these transistors, which is a current, hits the output capacitor which integrates it. So you have another low frequency pole and 90° more phase lag.

Thus the open loop has two low frequency poles, one from the opamp and one from the output cap, which means a phase shift of 180°. So it will be unstable by default. One solution would be to add a zero with the ESR of the output cap, another solution is to add a zero via compensation: in both cases you can place the unity gain crossover frequency where you want it with good phase margin.

However, the open loop gain depends heavily on the transconductance of the transistors, which is proportional to current, so it's going to move all over the place, and so will the unity gain crossover frequency. This is not compatible with a compensation (described in the above paragraph) that requires the unity gain crossover frequency to not move around too much.

So basically it's not possible to make this stable without a massive headache.

You have several options to make it much easier: