# Voltage reference vs voltage bias for EOG circuit

This is continuation of my previous question.

I'm confused about the reference voltage and bias voltage.

As seen in the image above, the supplies for the INA333 and OPA2335 are clearly 3.3V and ground. What confuses me is the Vbias and Vref on the non-inverting inputs and the reference pin on the INA333 - I was going to set that to ground but now I'm second guessing and wondering if I should add in a voltage reference IC to hold a constant voltage for the pins.

Are VRef and VBias even the same thing?

The other thing was why there was a potentiometer attached to the input on the second stage. According to the research paper this was taken from - "Another digital potentiometer, P2, is used to adjust the reference voltage of each channel". Are they saying this Vref is the same as the reference on the preamplifier (INA333?)

This was taken from the INA333 datasheet, showing an example ECG circuit, a similar topology was used for the EOG circuit. As you can see here, there is a series voltage reference outputting 2.5V, with a buffer. I don't get why they didn't just use the 2.5V output.

Anyway, this VBias as they call it is attached to the VRef (amplifier) and VBias (active feedback circuit.) The other difference is they use an integrator at the reference pin of the preamplifier instead of at the output. Is there a difference?

Core question:

• Are VRef, VBias, and the REF pin on INA333 the same thing? If not, why?
• How should I select what reference voltage (or bias, if they're the same thing) to use?

Extra questions:

• Why is there a buffer after the voltage reference in the second image?
• Is there a difference having an integrator at the REF pin of INA333 rather than connected to the output?

Is VRef, VBias, and the REF pin on INA333 the same thing?

No. In the top circuit, the band-pass section is AC coupled to the prior differential stage with capacitor C1. Everything following C1 operates about a mean of 0V, and it looks like $$\V_{REF}\$$ (in the top right "amplifier" stage, under control of P2) is intended to restore a DC offset to be compatible with the ADC.

In the lower circuit, there's no AC coupling capacitor, and every stage is directly coupled to the next. This requires that any persistent DC offset introduced anywhere in the chain (like the common-mode component, or input offset voltages, for example) must be cancelled in some other manner, lest that offset saturate the high gain amplifier stage. This is accomplished by integrator A4, which adjusts the REF input of the INA326 as a function of the difference between its mean output and $$\V_{BIAS}\$$. The INA326 output mean slowly converges to $$\V_{BIAS}\$$. The use of the OPAx335 is telling: that's a very low input offset voltage device, with low offset drift, and as an integrator it would be able to almost completely eliminate offsets introduced anywhere around the entire closed loop.

In the top "active feedback circuit" section, $$\V_{BIAS}\$$ seems to allow adjustment of common-mode body potential, but I'm not sure why that would ever be anything but right in the middle of the the common-mode input range of the INA333, so $$\V_{BIAS}=+1.65V\$$. It has nothing to do with any other biasing or reference potential in the system, and the label "REF" there should not be confused with $$\V_{REF}\$$ referred to in the "amplifier" section.

How to select what reference voltage or bias to use?

It seems logical to set $$\V_{BIAS}\$$ in the "active feedback circuit" to half of the supply, +1.65V. As I mentioned, I can't think why you would want to set a common mode potential different from that, especially considering that the INA333 input voltage range is almost to both supply rails.

$$\V_{REF}\$$ in the "amplifier" section would be chosen to suit your ADC. You would presumably want to place the signal mean half way between the lower and upper reference levels of your ADC. The relationship between input and output of that particular inverting setup is:

$$V_{OUT} = V_{REF}\left( 1+\frac{P_1}{R_4} \right) - V_{IN}\frac{P_1}{R_4}$$

Using this relationship, calculate $$\V_{REF}\$$ to centre the output according to your ADC's range. See my notes at the end, for more about this.

In the lower circuit, the entire system makes use of a single reference potential $$\V_{REF}\$$. The integrator uses it for centering the INA326 output around that potential, which means that A3 can also use it for its own bias. The common-mode body potential should be midway between the extremes of permissible input voltages for the INA326, which also happens to be about +2.5V. That second circuit really simplified things by requiring a single reference for everything.

Why is there a buffer after the voltage reference in the second image?

The REF3125 is quite noisy, at 48μV RMS, with noise power spread over a 10kHz bandwidth. A5 and its attendant resistor and capacitors form a low pass filter reducing bandwidth to 0.2Hz, which eliminates most of that broadband noise (and even $$\\frac{1}{f}\$$ noise), leaving behind less than a microvolt or so.

Is there a difference having an integrator at the REF pin of INA333 rather than connected to the output?

I'm not sure what you mean. You wouldn't connect REF to OUT, and you want the output to be an unaltered (except for amplitude) copy of the input potential difference, not an integrated version of it. The integrator is only there to remove any DC offset component present in the output, so that it remains centered around $$\V_{REF}\$$.

Some notes.

I don't think the first circuit is very practical. It serves well as a system block diagram, showing how the elements work together, and how they might be implemented, but it has flaws. In particular, using the +3.3V supply to provide offsets anywhere is just asking for trouble, since any supply noise will be injected into the signal path.

The second circuit doesn't rely on the supply potentials for anything other than supplying power, and supply fluctuations won't find their way onto the signal, to the extent that the PSRR of the various amplifiers attenuates them.

In the "amplifier" section of the first circuit, using P2 to generate a potential to raise the output seems like a bad idea. The gain of that stage is so high that even the tiniest fluctuation of $$\V_{REF}\$$ will ruin the signal. There are much better ways to achieve this goal. The second circuit doesn't even need such an offset, since the final amplification stage is fed with a signal already offset by +2.5V.

In the first circuit, C1 and R1 form a high pass filter, which removes DC offset:

simulate this circuit – Schematic created using CircuitLab

Source V1 produces a sinusoidal input of amplitude 2V, but with a DC offset of +2.5V, "shifting" it upwards to be centered about +2.5V on the graph below, shown in blue. The orange trace is the output, with that offset removed by the RC filter, and which you can see centered about 0V:

Consequently, the signal that emerges from the bandpass filter stage is centered about 0V, and goes both negative and positive. That may or may not be a problem for following stages, but if they require an always-positive signal (like the ADC, for instance) then further offset correction (biasing) will be required later on.

Here's a modification of the top circuit to use a common +1.65V reference for all modules:

simulate this circuit

The output of the "preamplifier" (differential) stage is the source of $$\V_{IN}\$$, and can have any DC offset, since that offset is removed by C1 and R1, and centered instead on a mean value of +1.65V. This ensures that the signal, all the way to OUT, is centered on +1.65V:

Importantly, the output (orange), centered around +1.65V, is now compatible with an ADC expecting a positive potential between 0V and +3.3V.

• A few things to clarify - "restore a DC offset to be compatible with the ADC", I thought the whole point was the remove the dc offset, why would they want to restore it? I don't get how the second circuit doesn't have any AC coupling with the capacitors on A3 and A4. "The integrator uses it for centering the INA326 output around that potential, which means that A3 can also use it for its own bias." - I don't quite get why they'd center output around 2.5V, and what it means for an amp to use it's own bias. Can you please elucidate. Jun 22, 2023 at 15:52
• Thanks for the detailed explanation though, provides a lot of learning. About making the first circuit more practical, as far as I understand, only the amplifier stage uses supply as offset, hence would doing what the second picture did (like an ldo or reference voltage) to provide the offset potential for the amplifier stage isolate supply? Any other ways to better implement the first circuit to make it more practical ? Jun 22, 2023 at 15:56
• @Roshan the second circuit centers all signals around +2.5V to avoid the need for dual supplies, like I just explained in my last comment. That may or may not be important or useful to you. The second circuit needs no AC coupling because all signals are centered on +2.5V. In the first circuit, the inputs to various stages have different DC offsets. By "its own bias" I mean that each stage has to be told (with an independent source of bias potential) what that offset is, in order to properly deal with it. Jun 22, 2023 at 16:13
• @Roshan, It's difficult to say whether you should update the question, because your new questions are somewhat unrelated to the original topic, and more related to sub-topics which may justify a whole new question! Anyway, for the DC offset removal of the RC high pass filter, I've updated my answer to demonstrate that behaviour. I suggest you use the simulator to get a feel for it. Click "Simulate this circuit" to play around. Jun 22, 2023 at 16:28
• @Roshan I didn't notice, what I've called C3 is actually Ct (it's so small and blurred I misread it), perhaps that's the source of confusion. Jun 22, 2023 at 16:53