I'm currently trying to understand SDRAMs at the example of the iS42/45S16320d and the DE10-lite board.
At the beginning of the sheet you can find a table "Key Timing Parameters" that contains some clock frequency values that seem "odd".
My question: the DE10-lite board has a base clock frequency of 50MHz. The both frequency values that are explicitly written down are 143 and 133 dependend on the CAS latency. My current understanding was that it's possible to run the memory at any frequency you want as long as you respect the minimum timing constraints.
Is it possible to use the base clock of 50MHz or do I have to use exactly 143 or 133MHz?
If 50MHz is possible, are there any consequences one should pay attention to according to the standard timings of the datasheet?
If no, why not?
If it's possible to run it at (almost) any frequency, what's the reason for these "odd" frequencies while the -5 variant names 200MHz and 100MHz?