# Understanding "Key Timing Parameters" of SDRAM datasheet

I'm currently trying to understand SDRAMs at the example of the iS42/45S16320d and the DE10-lite board.

At the beginning of the sheet you can find a table "Key Timing Parameters" that contains some clock frequency values that seem "odd".

My question: the DE10-lite board has a base clock frequency of 50MHz. The both frequency values that are explicitly written down are 143 and 133 dependend on the CAS latency. My current understanding was that it's possible to run the memory at any frequency you want as long as you respect the minimum timing constraints.

Is it possible to use the base clock of 50MHz or do I have to use exactly 143 or 133MHz?
If 50MHz is possible, are there any consequences one should pay attention to according to the standard timings of the datasheet?
If no, why not?

Bonus question:
If it's possible to run it at (almost) any frequency, what's the reason for these "odd" frequencies while the -5 variant names 200MHz and 100MHz?

• I don't see a link to the datasheet and I'm going to go look for it. It's been a long time since and things may be different today, but there was often a refresh counter built-in. If that's still true today, do you expect to use it? Or are you providing a row address from an external counter? Commented Jun 25, 2023 at 1:29
• Note that the fpga has plls that can synthesize a number of frequencies, so you’re not tied to 50MHz. The frequencies are the reciprocal of the 5,6,7ns values. Eg: 1/5e-9 = ?? Commented Jun 25, 2023 at 1:40
• @Kartman I know that I'm not tied to the 50MHz. To keep it simple I wanted to start with that without messing around with PLL at the same time. Commented Jun 25, 2023 at 13:22

The datasheet doesn't specify clock cycle time (tCK) max value, so there's no minimum clock frequency limit. So you can run at 50MHz.

Those '-5', '-6' and '-7' represents 'binning'. I presume that a part number will say something like iS42/45S16320d-5 or iS42/45S16320d-6.

'-5' parts are fastest part, so that you could raise your clock frequency up to 200MHz (you need to set the CAS Latency to 3). This is decreased to 167MHz for the '-6' bin (so the '-6' part should be cheaper than the '-5' parts.) As you are staying lower than the max frequency of the slowest part ('-7' part), you don't need to worry about the maximum side of the clock frequency at all, which means that you can use any setting (i.e. you can choose CAS Latency of 2, as it will give you better performance than 3).

For the CAS Latency of 2, it does look odd to me. My speculation is that they chose the way they screen parts like:

1. First they sort parts using CL (CAS Latency) of 3.
2. They also test all the parts using CL=2 at 100MHz.
3. For the parts that failed to be either '-5' or '-6' for CL=3, they do additional test using CL=2 at 133MHz.

So they tried to make the '-7' bin have its own value. So that '-7' bin doesn't necessarily be cheapest (as those who want to stick to CL=2, then '-7' bin is best as its max frequency is highest).

I think that this is probably because CL=2 and CL=3 have different frequency limiting points in the data path in their design, so max frequencies of CL=2 and CL=3 probably have low correlation (almost independent).