EP to ground symbol from Maxim Integrated Reference Design 1104.
Appears to be a net tie.
From the PCB layout document:
I'm guessing the designators a bit, as they don't give an assembly drawing.
Note that the input terminals (large oval pads in the left corners) connect to top-side pours with bypass capacitors nearby (C1?), but the bottom one (C2?) does not, and instead has a via to an inner pour (Mid2). The negative terminal also connects to Mid1 (PGND plane), and there are additional bypass caps on the bottom side.
The controller's exposed pad doesn't show a via in it (the pads overlap and the drill layer isn't shown here), but there is, in fact, a single via there. It seems this via is configured as a net tie, as evidenced by the two mid layers connecting differently. We can deduce Mid1 is PGND, and Mid2 is SGND (or whatever they call them here). On the bottom, the via is also used to ground R1 and C13.
This strategy is often proposed in application notes, but never (as far as I can recall) discussed quantitatively, and I have not seen any value in the practice myself. It is generally better and/or easier to separate current loops, than to waste an entire layer that, given its area, will couple strongly with the very things that it's supposed to be avoiding.