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[EP to ground symbol from [Maxim Integrated Reference Design 1104]]

EP to ground symbol from Maxim Integrated Reference Design 1104.

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  • \$\begingroup\$ drive.google.com/file/d/18le1P3C-y5f-MNeRr5g5TiyqBwfh5lP6/… \$\endgroup\$ Jun 25, 2023 at 16:16
  • \$\begingroup\$ All there is is a zip file which phone says it can't open. Please link to an actually openable file and state what page the symbol is on. \$\endgroup\$
    – Justme
    Jun 25, 2023 at 17:38
  • \$\begingroup\$ Apologies, didn't think of mobile. Here are the PDFs individually linked, though I think @TimWilliams has the answer. Schematic: bit.ly/max1104sch PCB: bit.ly/max1104pcb BOM: bit.ly/max1104bom \$\endgroup\$ Jun 26, 2023 at 5:26
  • \$\begingroup\$ F and S are Force and Sense -- terms taken from Kelvin 4-wire connections. \$\endgroup\$
    – david
    Jun 26, 2023 at 6:27

2 Answers 2

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Appears to be a net tie.

From the PCB layout document:

maxrefdes1104 Top Zoom
Top

maxrefdes1104 Mid1 Zoom
Mid1

maxrefdes1104 Mid2 Zoom
Mid2

maxrefdes1104 Bottom Zoom
Bottom

I'm guessing the designators a bit, as they don't give an assembly drawing.

Note that the input terminals (large oval pads in the left corners) connect to top-side pours with bypass capacitors nearby (C1?), but the bottom one (C2?) does not, and instead has a via to an inner pour (Mid2). The negative terminal also connects to Mid1 (PGND plane), and there are additional bypass caps on the bottom side.

The controller's exposed pad doesn't show a via in it (the pads overlap and the drill layer isn't shown here), but there is, in fact, a single via there. It seems this via is configured as a net tie, as evidenced by the two mid layers connecting differently. We can deduce Mid1 is PGND, and Mid2 is SGND (or whatever they call them here). On the bottom, the via is also used to ground R1 and C13.

This strategy is often proposed in application notes, but never (as far as I can recall) discussed quantitatively, and I have not seen any value in the practice myself. It is generally better and/or easier to separate current loops, than to waste an entire layer that, given its area, will couple strongly with the very things that it's supposed to be avoiding.

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This is a bottom TQFN package exposed thermal pad connected to a hot GND. EP = Exposed Pad.

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