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I just watched Adrian (of Adrian's Digital Basement channel) demonstrate a level shifter for an 80s computer using only diodes and resistors. I attach a frame with the schematic below; can someone please explain how this works? Left side is the 5V side, right side is the 3.3V MMC card side.

Schematic of level shifter

My pathetic attempt (SW engineer here, go easy):

Option 1

  • The voltage regulator turns the 5V into 3.3V (red line) and powers the MMC.
  • When the MMC card's SDO output (3.3V output side) emits high (3.3V) the diode blocks us. I see a pulldown past the diode; the green line is supposed to be the common GND. So the CB2 (5V side input) gets "low" - maybe this is reverse logic...?
  • When the MMC card's SDO emits low (0V), I see nothing from the left side driving the diode. How is CB2 supposed to rise high? (Assuming we are indeed reverse logic)...
  • The other direction is just as mysterious to me. If PB0 emits low, OK, things are simple; SDI gets a nice low. But if PB0 emits high (5V), the 3.3V input side is supposed to somehow get something close to 3.3V. How? The SDI (I am guessing) is not supposed to sink current - so only the left 4K7 is consuming the 5V; and the SDI should be seeing 5V (which is bad for a 3.3V input).

Option 2

Perhaps the schematic is swapping inputs with outputs; i.e. CB2 is output-ing either 0 or 5V; and PB0 is expecting to read either 0 or 5V.

  • If CB2 emits 0V, the diode is asleep, and there's a pull up on the other side, so SDO sees 3.3V. Hmm, maybe this is reverse logic...
  • If CB2 emits 5V, the 4K7 on the left gets a cozy 1mA to GND that seems useless... On the right, the diode conducts, drops 0.7V, so SDO sees 4.3V (far above the 3.3V we're supposed to send it)... and definitely not "reverse logic" 0V. The 4.3V - 3.3V = 1V difference also drives a small current through the right-hand side 4K7 into the 3.3V. That doesn't seem right...
  • In the other direction, if SDI emits "low", PB0 sees "low". But if SDI emits "high" (3.3V) there is a voltage divider that makes PB0 see 1.6V...

In plain words, none of the two interpretations seems to makes sense... And yet, Adrian reports the circuit worked fine.

Help?

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3 Answers 3

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It's unclear whether the 3.3 volt device will survive: -

enter image description here

If 5 volts is applied as shown in red on the left, there will be an open-circuit 5 volts on the right (in blue) so, if the 3.3 volts device can clamp the injected current and limit the voltage to 3.3 volts (or thereabouts) and, survive the injected current (0.319 mA) then it should be OK.

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  • \$\begingroup\$ Thank you, Andy. That was my understanding as well: "The SDI ... is not supposed to sink current - so only the left 4K7 is consuming the 5V; and the SDI should be seeing 5V (which is bad for a 3.3V input)". But if the device is indeed 5V tolerant, isn't all this pointless? What's the point of the diode? If we were to protect the 3.3V side it should be looking the other way... Or what is the point of hooking the 5V points in between 4K7 resistors? Overall, very confusing circuit - at least to me. \$\endgroup\$
    – ttsiodras
    Commented Jun 25, 2023 at 18:58
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    \$\begingroup\$ For SDO (right hand side) to transmit to the left all looks a mess to me. \$\endgroup\$
    – Andy aka
    Commented Jun 25, 2023 at 19:00
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The 5V->3.3 may not be a voltage divider as claimed by the video- but it may work, as Andy has explained. That's assuming the firmware uses outputs conventionally and doesn't so something like switch between input and '0' out. In that case it would be a voltage divider between the input pullup depletion-mode MOSFET and the 4.7k resistor, with the other 4.7k resistor in series for insurance.

The Beeb inputs are specified at 0.4V for '0' and 2.4V for '1', I believe (NMOS .. not modern CMOS .. TTL-like). The depletion-mode MOSFET load (pullup) that sources about 1mA typically with output at 400mV. Certainly with the diode in series it can't possibly meet the 400mV input specification at all. But it may well work. I don't see any typical input transition voltage for the relevant chip (6522 VIA).

enter image description here

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If this circuit actually allows the intended communicatations it is by accident. I suspect that this is not the actual circuit and was published by mistake.

Note the comment: As-built drawing - Note I built this board without planning its layout first.

There are two main problems:

  1. The entire ciruit between the MMC and the Port should be flipped.
  2. As pointed out in the OP, there is no 5V source for for the 5-Volt input. BUT, the port input circuitry probably has TTL thresholds, so 3.3 volts is probably sufficient.

The specs for a typical MMU interface are shown for a Samsung product. An image of the relevent data is shown below.

enter image description here

Using the data presented, the input thresholds resemble TTL levels, so any voltage over 2.0 volts will register a HI.

Elsewhere in the datasheet specified the maximum input voltage at 3.6 V.

My version (I didn't test it) is presented below:

enter image description here

R1,R2 and R5,R6 scale SCLK and SDI respectively to 2.5V, which is sufficiently above the 2.0 volt TTL threshold.

SDO can be either open-collector or push-pull. R4 is required to pull up the open collector to source a voltage to CB2.

D1 is used to prevent 5V transients from reaching the SDO pin. So R3 is required to pull CB2 low. The values for R3,R4 must be chosen to minimaly scale 3.3V to about 2.5V while considering the diode drop.

Speed is not a concern as long as switching times are maintained. This Samsung MMU is fully static so can operate at the low speeds of the day.

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