Why is the data type of the input inside the module and the output outside the module fixed to net
For the inputs, in the context of the module being described, there is no always or initial block assigning to that variable. Therefore it is not a reg.
For the outputs, as far as the module that instantiates your module is concerned, again there is no always or initial block assigning to that variable. So again it is a wire and not a reg in that context.
Basically the only difference between a wire and a reg is that a reg is assigned to in an always or initial block, and a wire is assigned to in an assign statement, or as an output of a sub-module.
So the "external component" of a modules outputs are this author's name for the way the outputs are seen when a higher level module instantiates your module. Since these nets in the higher level module are assigned by the output of a sub-module, they must be wires and not reg's.
How do I decide whether to use a register data type or a net data type when it is not already fixed
If you are going to use an always or initial block to assign the values of that net, you must declare the net as a reg.
If you are going to use an assign statement or the output of a sub-module to assign the values of the net, you must declare the net as a wire (or one of the other wire-like types). In the case of sub-module outputs, the internal design of the sub-module, and how the sub-module declares or assigns the variable, does not matter --- only that, in the context of the module you are writing, the variable is assigned by the output of a sub-module.
And some simulators and synthesis tools won't even enforce those restrictions, making the difference between reg and wire entirely irrelevant as long as you only use those tools.
