# What exactly happens at the fundamental level if base voltage is higher than collector voltage in CE transistor?

In the first answer to this question, it is stated that:

This happens even if the base and collector are at the same voltage (!). Basically, one way to model a transistor is as the base-emitter diode, which is forward biased in normal operation, and the base-collector diode, which is reverse biased in normal operation, and a magic current source that causes 99% of the emitter current to flow from collector to emitter.

If the collector voltage drops below the base, the transistor will still amplify current -- at this point, the base-collector diode is forward biased, with some current flowing in it, but that action can still be overwhelmed by the "magic current source". In fact, this is a useful mode of operation, where in a typical 1970's-era transistor like the 2N3904, you can have a current amplification of 10:1 or so when the collector-emitter voltage is 0.2V. In new "super-beta" transistors you can get useful amplification with this voltage less than 0.05V.

What I don't understand is this: shouldn't the base-collector junction be reverse biased in active mode? What happens at the fundamental level to the charge carriers if the junction is forward biased?

By the way, I'm simply a high schooler trying to learn this stuff, any help would be greatly appreciated.

What I don't understand is this: shouldn't the base-collector junction be reverse biased in active mode?

When the base-collector junction is forward biased (and also the base-emitter junction) the transistor is (generally) said to be in the saturation region.

There is some variation in terminology used, but if the base-emitter and base-collector voltages are considered to be axes on a graph, then the active region is in one quadrant and the saturation region in another quadrant.

What happens at the fundamental level to the charge carriers if the junction is forward biased?

If the base-emitter and base-collector junctions are both forward biased, primarily what happens is this: Majority carriers cross the emitter and reach the base-emitter junction. They cross the junction and become minority carriers. Because the base is much more lightly doped than the emitter, there are a relatively larger concentration of minority carrier in the base than majority carriers. These minority carriers thus have a relatively long lifetime before recombining. Most of these minority carriers this reach the base-collector junction. Many pass over this junction and become majority carriers again in the collector. They continue on, crossing the collector and either reach the electrode and enter it, if they are electrons, or recombine with electrons near the collector electrode if they are holes.

what if the voltage difference between the forward base- collector junction is less than the depletion voltage? Shouldn't then the flow of current stop between base and collector?

If the emitter is left disconnected, and the base-collector junction is used as a diode, then significant conduction will not occur until there is sufficient forward voltage across the base-collector junction. What is "sufficient" is not well defined, but 0.6, 0.65 and 0.7 V are often taken to be the forward voltage of a conducting Silicon PN junction. In reality there is no exact voltage where the junction suddenly turns on.

The situation where the emitter-base junction is different from the case where the emitter is left open. When the emitter is left open, it is majority carriers that dominate in the base. These majority carriers will not cross a PN junction in large numbers until the forward voltage is sufficiently large.

However, in the case where there is a sufficiently large forward bias in the base-emitter junction for ther to be significant emitter current, the base is mostly populated with minority carriers, not majority carriers. The minority carriers easily pass across the base-collector junction, even though the forward bias is small (or even negative!). That is how minority carriers interact with PN junctions.

• Thank you for the answer! However, I have one question: what if the voltage difference between the forward base- collector junction is less than the depletion voltage? Shouldn't then the flow of current stop between base and collector? Commented Jun 26, 2023 at 19:23
• I expanded my answer to address your most recent comment. Commented Jun 26, 2023 at 19:50

Very short answer (Einstein: Explain everything as simple as possible - but not simpler):

When the base potential exceeds the potential at the collector, the B-C pn junction is forward biased (in contrary to "normal" amplifying operation). As a result - there is a heavily increased current into the base (through BOTH pn junctions). This situation gives the DEFINITION OF SATURATION.

Note: The increased base current is the RESULT of saturation and, hence, a safe indication for saturation but not its cause (as we can read in some books and other contributions).

Consider the NPN transistor. It is constructed of N-P-N layers, that is, roughly symmetrically.

Real parts aren't symmetric for a number of useful and practical reasons (VCE(sat), gain, breakdown voltages, speed, etc. are all affected), but let's stick with this for now and see where it takes us.

Suppose we ground one N-layer (emitter), connect positive voltage to the other (collector), and apply a bias current to the P-layer (base). As if by magic, current is drawn through the collector, at IC = IB hFE.

Note that hFE need not be constant; we're not saying this is a ratio that must hold, simply that the currents are nonzero and therefore a ratio exists. More particularly, hFE > 0 for the most part; and when it's not positive, we shall transform the circuit, so that either hFE doesn't apply, or an alternative definition applies.

If we swap around which N-layers we're biasing, we get the same thing; nothing has changed. But we have swapped terminals, so we call it "inverted operation". If we keep terminals labeled the same way, with the same current directions, we instead have IE = IB hFE(R). But for a perfectly symmetrical transistor, this is simply swapping C and E, which are identical, so we would have hFE = hFE(R).

Now, suppose the transistor is not symmetric. The forward and reverse hFEs will not match, among other things. But we still get, erm, transistance, where collector current flows as a consequence of base current. The amount varies between configurations, but not the phenomena itself -- it suffices that it's still a transistor, whether inverted or not.

Let us also consider the case for both N-layers grounded. That is, VCE = 0. In this case, regardless of any "transistance" that might happen (and indeed, since the situation is perfectly symmetrical, any induced C-E current must balance to zero), and we can draw an equivalent circuit like two diodes in parallel. If instead of hard-ground, we vary the collector voltage slightly, we unbalance the diode pair, and so for small changes (perhaps 10s of mV), and the C-E characteristic looks like a resistance.

However, if we raise the C-E voltage further (or E-C, as the case may be), the diode equivalent fails, as current reverses (i.e., hFE or hFE(R) > 0), and we observe transistor action again.

And, we can indeed understand operation as if the B-C junction were a diode stealing base current from the B-E path, sneaking it into the collector path, reducing hFE, and approaching that "two diodes in parallel" equivalent circuit. Those two diodes are always there, of course, it's just that we normally reverse-bias one. Indeed, VBE drops ever so slightly in saturation, so it's even a measurable external effect.

As you continue your studies, you will encounter the Ebers-Moll model: mind that this is only valid in the linear range (VCE > VCE(sat)), and is meaningless in reverse (that is, inverted). It's an excellent description of the phenomena of "transistance" in this condition -- but it's far from a general description, as you can see. Input values outside the intended range and you get garbage. Well, there exists a more general model -- it's harder to work with so you wouldn't want to be working problems on pad and paper for example, but for computational purposes, it's valid for any combination of terminal voltages and currents. The most common such model is the Gummel-Poon model; this is used by most SPICE simulators. Some of the parameters of this model are indeed the forward and reverse hFE (BF and BR in SPICE).

So, in summary: what happens at low VCE, is continuous from low negative to low positive VCE; and it can be understood as hFE falling (as VCE falls, entering forward saturation), the junctions acting like diodes shunting base current (VCE near zero, in deep saturation), then hFE(R) taking over, and rising again (as VEC rises, out of inverted saturation).