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The power supply decoupling capacitors are supposed to have as less ESR and ESL as possible. I can find capacitors by typing something like ceramic capacitor, tantalum capacitor etc. but how do I look for specially designed low ESL and low ESR capacitors that are for use in power supply decoupling in a seller’s website?

This is for use with CPLD and FPGAs.

EDIT:

Please see this excerpt taken from a catalogue of capacitors. These images are from a catalogue from Samsung Electro-Mechanics. I found a catalogue from Kyocera that is similar.

enter image description here

The basic question is, how does one search for these special kind of capacitors? I don't think just using "MLCC" will help. I thought that power supply decoupling should be done using the special capacitors to get the best result.

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  • \$\begingroup\$ What is your application? I’ve characterized a wide range of capacitors to about 110GHz and, depending on what I’m doing with them, I have used varying ways to select them. Bottom line - the data sheets have virtually never been useful due to difference in their layout vs mine. Their extraction methods often include board pad capacitance, sometimes improper de-embedding. At the end of the day I buy some and measure them. \$\endgroup\$
    – 65Roadster
    Jun 28, 2023 at 13:20
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    \$\begingroup\$ The fact that they say low ESR, low ESL… it’s not really that meaningful. It’s just bullets on a datasheet which a marketer put on, it’s not an objective measure. \$\endgroup\$
    – 65Roadster
    Jun 28, 2023 at 13:20
  • \$\begingroup\$ The topic is decoupling capacitors for FPGA and CPLD. I am electronic engineer by profession specializing in ASIC/FPGA Digital Design and Verification and am trying to get proper understanding of PCB design. \$\endgroup\$
    – quantum231
    Jun 28, 2023 at 14:43
  • \$\begingroup\$ @quantum231 If you want to learn how to decouple advanced logic designs you should get a book on that topic, watch lectures, read white papers from your suppliers, and study your datasheets. Then, you can use the parametric search to find the parts you are looking for, but the digikey search cannot itself make design choices for you. You have to understand what you're doing and then use your knowledge to search for the correct parts. It seems like you're hoping for a shortcut that will avoid having to do design work yourself. No such luck! \$\endgroup\$ Jun 28, 2023 at 15:44
  • \$\begingroup\$ I need to know what to look for before I start looking, vague terms do not help. \$\endgroup\$
    – gyuunyuu
    Jun 29, 2023 at 8:30

5 Answers 5

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In general, any ceramic capacitor has low ESR (equivalent series resistance) and ESL (equivalent series inductance). There are special geometries that provide lower ESL by having the terminations on the long-side of the part. X7R ceramic is a good compromise for capacitance voltage sensitivity (capacitance reduces with applied voltage for class 2 ceramics). Stick with the smallest package to minimize ESL. If you need better information on ESR & ESL you need to measure this on a swept impedance analyzer. Kemet K-SIM (Web site) is a good tool for sussing out capacitor specifications. That said, I have found typical data on manufacturer web sites to be off by a significant amount which is why I have sweeps of the capacitors we use in house.

Also important is the PCB layout and where you place vias for the capacitor. Xilinx has good information in their documentation on bypassing, such as UG483.

For electrolytic capacitors, those that are designed for switching power supplies is a good marketing term to search for as these are designed for low ESR and high current. These will be radial capacitors (stand-up style). From personal experience avoid using cheap Chinese capacitors as these have lifetime issues as evidenced by the amount of gear I have repaired. ESL is generally not stated for electrolytic capacitors, thus, you need to measure this on an impedance analyzer or make an assumption based off measuring the resonant frequency of the capacitor.

If you use tantalum capacitors, stick to polymer tantalum as they are more rugged wrt current surges and they don't catch fire if severely tortured. Standard tantalum capacitors are sensitive, as in failure, to inrush current - especially during power-up.

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  • \$\begingroup\$ Is "impedance analyzer" the same thing as network analyzer that gives us the S parameters? \$\endgroup\$
    – quantum231
    Jun 28, 2023 at 10:54
  • \$\begingroup\$ "Stick with the smallest package to minimize ESL.". True, but the smaller the package, the higher the voltage sensitivity. \$\endgroup\$
    – RussellH
    Jun 28, 2023 at 12:31
  • \$\begingroup\$ @quantum231 An impedance analyzer, such as an HP4194, is designed to measure impedance over a very wide range, from milliohms to megohms. While you can use a network analyzer to measure impedance, they typically don't have the impedance measuring span that a dedicated impedance analyzer has. \$\endgroup\$
    – qrk
    Jun 28, 2023 at 16:26
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Murata has a nice website for this:

https://ds.murata.co.jp/simsurfing/index.html?lcid=en-us

Then you can plot ESR, ESL, Z, etc versus frequency, loss of capacitance of your MLCCs versus applied DC voltage, etc.

However...

A ceramic cap isn't very useful unless it's soldered on a board, and then the total inductance must include vias or other copper in the circuit. So the number from the manufacturer says something, but it's not the whole story.

Regarding inductance, MLCCs are pretty simple, they're a stack of plates in a tiny box so they'll have the same inductance as a chunk of metal the same size as the capacitor soldered on the board in the same place. So it pretty much depends only on package.

For example the "reverse geometry" caps with the contacts on the long end have lower inductance because of the shape. But that won't reduce the inductance of your vias, and it's the same as putting two smaller "normal" caps next to each other while being more expensive.

If the cap that has half the inductance (mounted) is three times as expensive as the jellybean cap, just put two jellybean caps in parallel.

Now think about a row of caps on your PCB, look at it from above the board and stick a "+" where the current goes up in a via and a "-" where it goes down the via into the board. A neat row of caps will look like this:

++++
----

Some clever caps like X2Y or the IDC ones you put in your screenshot reduce the inductance of your vias, by letting you arrange the vias in a criss cross pattern where the direction of current alternates:

+-+-
-+-+

So the magnetic fields from these loops cancel and that reduces the total inductance including the vias. It's pretty neat.

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    \$\begingroup\$ +1 for the "metal block" analogy. basically, the proximity of the bottom face of the component to the board determines ESL. Any flat MLCC with a given footprint and via pattern sitting right on the board, has the same ESL regardless of its height. Vertically stacked caps are actually worse for ESL (better ESR) because their J lead bracket raises them from the board. \$\endgroup\$
    – tobalt
    Jun 28, 2023 at 16:13
  • \$\begingroup\$ Yes, it's the same for resistors. Usually the resistive layer is on top, so the thickness of the ceramic body raises it from the board. There's a measurable decrease in inductance if the resistor is soldered upside down! Only matters for very low values of course. \$\endgroup\$
    – bobflux
    Jun 28, 2023 at 20:17
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ESL is determined by the capacitor package rather than its type, so you would pick a capacitor package with sufficiently low ESL for the application. Generally for advanced logic devices where this matters the vendor will describe in great detail what packages have acceptable ESL. For advanced FPGAs, this documentation can run for hundreds of pages.

Decoupling capacitors for logic devices are virtually always MLCCs, which have negligible ESR, so this is not something you would specifically search for.

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  • \$\begingroup\$ It's not the package, it's the current loop, including vias, planes... The package is only a small part of this. The via pattern is much more important. Tight between-pads vias in a 1206 have lower ESL than far-side vias for a 0603. \$\endgroup\$
    – tobalt
    Jun 28, 2023 at 16:06
  • \$\begingroup\$ @tobalt Sort of. Once you go to really low ESL packages you have to consider the net magnetic field sumed over all loops, since things like IDCs arrange opposite loops (and vias) to cancel out magnetic fields. In that case package will matter a lot (but so does layout of course). \$\endgroup\$ Jun 28, 2023 at 16:56
  • \$\begingroup\$ Yes, what I wrote above is for simple two-terminals caps. \$\endgroup\$
    – tobalt
    Jun 28, 2023 at 17:03
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At least from the two documents, the Kyocera has impedance curves and some models are specified as low ESL.

Some diagrams show how the curve varies between package.

Some manufacturers (e.g. Murata) have a tool on their website where you can see the impedance curve of the capacitor, and the curve may be available on product specific data sheet as well.

As those all are ceramic SMD capacitors, they might in general have already quite low ESR and ESL, but there are ceramic caps that have terminals on the wide edge and they have even lower ESL. So it might very well be that standard ceramic caps already have low enough ESR and ESL for generic purposes.

For electrolytic caps, some are rated as low ESR, and polymer electrolytics have low ESR anyway compared to standard ones so it might not need special advertizing.

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  • \$\begingroup\$ Lets say you got a website like farnell, digikey or mouser. How would you search for these special type of capacitors? \$\endgroup\$
    – quantum231
    Jun 28, 2023 at 14:45
  • \$\begingroup\$ @quantum231 On digikey the parametric search term is called "Package / Case". From that you can select the appropriately low ESL type. \$\endgroup\$ Jun 28, 2023 at 14:50
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Below is how we think about this in 100G to 200G bypass applications.

The most important factors will probably be capacitor placement, PCB stackup, and ground routing. I see much less difference from one capacitor to another.

As a reference, I characterized 0.1uF capacitors to 80-110GHz and saw very little difference between a dozen randomly selected 0.1uF parts from Digikey, even when compared to very high dollar boutique capacitors.

0201 was much better than 0402, which was better than 0603, etc. Smaller case size was almost 100% guaranteed to be better than larger, regardless of what cap you pick.

PCB stackup and capacitor placement are the dominant factors.

ESL quoted by vendors is not accurate and not helpful. In particular from one vendor to another, the methodologies to measure and de-embed, and what is de-embedded, and the quality of work is highly variable. I’m not sure I know any high speed folks who really even pay any attention to that kind of vendor info.

Also, many ASIC/FPGA vendor app notes use antiquated rules of thumb which don’t hold (e.g. the 3 capacitor myth).

I’d highly recommend watching videos by Eric Bogatin and Rick Hartley to get some really good illustrations and explanations of how to handle bypassing.

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  • \$\begingroup\$ Did you use smaller via patterns for smaller packages? Did you counter-try those same smaller via patterns for large packages, too? \$\endgroup\$
    – tobalt
    Jun 28, 2023 at 20:02
  • \$\begingroup\$ I apologize for a (very) tardy response here. I am generally forced to use small vias due to I/O density. There are some papers out there which show vias on the side of capacitor pads for improved effective ESL. That makes sense to me but I've never characterized that myself to have a feel for whether that difference is material. \$\endgroup\$
    – 65Roadster
    Sep 8, 2023 at 19:18
  • \$\begingroup\$ What I mean is that, IMO, the difference you saw between the package types is to a large extent because you have used tighter via placement for smaller packages, not from the package per se. If you place a 0603 and fit both vias underneath it between its pads, its ESL will be far smaller than with vias beyond its pads or even vias on the side. \$\endgroup\$
    – tobalt
    Sep 9, 2023 at 6:20
  • \$\begingroup\$ I’d agree with that. It’s the loop size that matters, and to whatever extent you can decrease that with case size and via placement, it’s going to help. Most of the time I’m doing chip-on-board with a cap top side next to the die. The ground is the first buried layer, 4mil down. So my loop is the bond wire to the PCB, to the cap, through the GND via, back up under the die and then to backside of die. Case size is inline with the loop and matters. But often having via-in-pad also shrinks the loop. Since I always use via-in-pad, the case size is really pushing my loop size. \$\endgroup\$
    – 65Roadster
    Sep 9, 2023 at 7:35

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