I have a counter made of several FFDs (see image below and please ignore R wire):
Def: N(t) - Signal N at time t, where t is a real value and 1 CLK cycle = 2t units. This will be important further.
Def: E_i - Element E at stage i.
As every Q{i} output will feed into the clock input of the next FFD{i+1}, it is a simple Asynchronous Ripple Counter. Also, in theory, at every stage it should halve the clock frequency compared to the previous stage.
CLK_0 = f (system clock frequency at stage 0)
CLK_1 = f/2
CLK_2 = f/4
...and so on
Will this counter be usable in a synchronous system with a CLK = f? Will it be able to write out values with the right timing?
Consider this example, where I have extracted first 2 stages of the counter:
t = 0: at time t = 0 we have following configuration:
Q_0 = 0 & !Q_0 = 1
Q_1 = 0 & !Q_1 = 1
FFD_0 = 0
FFD_1 = 0
CLK_0 = 0
CLK_1 = 0
t = 0.9: first flip flop has already read the new value but the output Q_0 hasn't yet settled. Also, whoever was reading Q_0 and Q_1, read 0 on both. So we have this configuration:
Q_0 = 0 & !Q_0 = 1
Q_1 = 0 & !Q_1 = 1
FFD_0 = 1
FFD_1 = 0
CLK_0 = 0
CLK_1 = 0
t = 1.1+: The clock edge stared to fall but it is not yet 0. FFD_0 outputs have settled and FFD_1 is receiving rising clock edge from Q_0 and it is reading !Q_1 (this is Q_1 bar). It looks like here:
Q_0 = 1 & !Q_0 = 0
Q_1 = 0 & !Q_1 = 1
FFD_0 = 1
FFD_1 = 0 (reading in progress)
CLK_0 = 1 (falling)
CLK_1 = 1
t = 2: By this time, all values have settled:
Q_0 = 1 & !Q_0 = 0
Q_1 = 1 & !Q_1 = 0
FFD_0 = 1
FFD_1 = 1
CLK_0 = 0
CLK_1 = 1
At this point here's the issue: CLK_0 = 0, which is also same as system clock. By the time CLK_0 = 1 we have Q_0 and Q_1 both equal 1. So, whoever reads counter output, reads it in sync with CLK_0. Apparently, it will receive following value:
00 -> 11 instead of 00 -> 01
Now, if my counter had Q_0 settled by the time t=3 (2nd clock edge), everything would work perfectly. But, at this point I don't think it happens. I have CLK_0 as system clock but CLK_1 is triggered as soon as Q_0 settles.
Is it even possible to use this counter in a synchronous circuit? Do I have to make changes? Or should I simply go for a synchronous variant?