I'm experimenting with a learning project, where I want to generate a "reset pulse" (from high-low-high) to trigger a reset of a microcontroller, an ESP8266. This is the only way to wake this chip from deep sleep (hard reset). Disclaimer: I know about the more powerful ESP32, but I still want to try to understand why this setup is not working before moving on ;)

So the idea is to trigger a mosfet on every button state change, both when it goes from open to closed (0 to 3.3V), and when it goes from closed to open (3.3V to 0). To achieve this, I've got some help on ##electronics to set up the following simulation

enter image description here

Consider both switches of "SW1" to open and close simultaneously (doesn't have to be exact timing). This is for a simple door sensor, so I couldn't easily use a DPDT switch. And in any case, please refer to my above disclaimer whenever this seems over-engineered or just odd. I just want to learn why this is working (very much) different in real life, than in the sim.

In the sim, the drain of the mosfet stays at VCC while the mosfet is off, and goes to 0 while it is on, giving a nice high-low-high pulse. In my actual setup, I have only 0.6V at the drain when the mosfet (BS170) is off. Is this mosfet very different from the one set up in the sim? As it seems to me, this voltage is pulling the RST pin of the ESP low at all times so it just never runs.

Components used are:

  • 3.3V power supply
  • BS170 N-channel mosfet
  • 2.2nF caps (I didn't have 10uF ceramic ones)
  • 1N4001 diodes

Actual setup

Yellow: gate voltage (button click), blue: drain voltage (0.6V to 0)Yellow: gate voltage (button click), blue: drain voltage (0.6V to 0)

Updated schematic after answers below:

enter image description here

  • 1
    \$\begingroup\$ You've maybe got drain and source swapped on your real circuit. \$\endgroup\$
    – Andy aka
    Jun 29, 2023 at 8:48
  • \$\begingroup\$ Pretty sure that's not the case... I've added a photo of my actual setup :) \$\endgroup\$
    – joakimk
    Jun 29, 2023 at 9:04
  • \$\begingroup\$ Following on from Andy's suggestion are you sure it is a BS170? Other similar devices have the drain and source swapped. (eg st.com/resource/en/datasheet/cd00005134.pdf). Why not just try rotating the device 180 deg. It is acting as if it is wired backwards. \$\endgroup\$ Jun 29, 2023 at 9:19
  • \$\begingroup\$ You can pull your NMOS out of your circuit, measure if there is a diode between source and drain, to make sure if your NMOS is working fine. \$\endgroup\$
    – Willis Lin
    Jun 29, 2023 at 11:45
  • \$\begingroup\$ The component is marked "BS 170 QG 95". Rotating it 180 deg does indeed bring the drain (which I assumed was the source) up to 3.3V, as expected. So strange, as all image search on "BS170 pinout" identify the pins the other way around \$\endgroup\$
    – joakimk
    Jun 29, 2023 at 12:27

1 Answer 1


Is this [MOSFET marked BS170] very different from the one set up in the [simulation]?

The simulation uses a \$V_{GS(th)}\$ of 1.5 V.
According to the onsemi datasheet, the gate voltage \$V_{GS(th)}\$ for 1 mA drain current with \$V_{DS} = V_{GS}\$ is 0.8 V min/2.1 V typ/3 V max.
A design should work for all devices within the specified range of device parameters.

The behaviour you describe (0.6 V max) is typical of a MOSFET with drain and source swapped and body diode conducting; the oscillogram is even more telling:
For a short time, \$V_{GS}\$ is high enough to lower the channel resistance for an even lower output voltage.

From steady state, opening the upper contact lets a 1k resistor pull down the left side of a capacitor "clamped to ground" with a diode on the right:
The right side will drop to the diode's forward voltage for the decaying current.
Closing the contact yanks the left side to 3.3 V resulting in 3.3 V (- Vf) peak on the right.

Opening the lower contact lets current through the 1k pull-up flow through the capacitor and a 1k pull-down to ground, both resistors effectively a voltage divider:
The voltage peak at the pull-down will be 1.65 V with a capacitor initially discharged.
For a decent peak voltage, the pull-down's value needs to be considerably higher than the pull-up's.

From the peak voltages there is another diode drop to consider for "the OR-diodes".

I don't understand "fulstad's" simulation result for closing the lower contact.

I can't imagine any amount of parameter adjustments turning this diode OR + MOSFET into a reliable reset generator, let alone with the requirement
both when it goes from open to closed, and when it goes from closed to open.


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