1
\$\begingroup\$

I have been working on a communication link between an FPGA and a SPI slave. The electrical connection between the two is done via a 2 metre cable composed of 42AWG wires with the following characteristics, as shown in the datasheet:

  • Conductor: 7/0.025 (<-What does this mean?) Silver copper alloy
  • Insulation: PFA 0.19 diameter
  • Wire resistance 7000 MAX (<-what does this mean?)
  • Characteristic impedance: 50 ohm

Looking at an old coworker's notes, the capacitance per meter found is 110pF/m.

In order to measure the impact of the cable's length on the SPI link, I created a RLC model (see figure 1.) Since the characteristic impedance of the cable is 50 ohm, I inserted a 50 ohm resistor at the output of the FPGA.

I ran some simulations and noticed some reflections on the signal (the normal, I guess.) Out of curiousity, I re-ran the simulation with a 100 ohm output resistor and it improved the quality of the pulsed signal. See the following figures for reference.

  • 50 Ohm simulation

enter image description here

enter image description here

  • 100 Ohm simulation

enter image description here

enter image description here

Now going to the question (as the title says):

Must the output impedance match the cable's characteristic impedance? If not, how do I determine/approximate the right value?

\$\endgroup\$
4
  • 1
    \$\begingroup\$ R1 should not be 1g for the SPI slave (?). \$\endgroup\$
    – Antonio51
    Jun 30, 2023 at 10:04
  • 3
    \$\begingroup\$ (1) why don't you use LTspice's inbuilt t-line component instead of making a poor approximation with lumped lines. (2) I have no idea what the red and blue traces represent. (3) very difficult to see the blue (whatever that is) waveform on a black background. (4) You can set the background to be white. (5) link the data sheet for the cable. (6) Draw how clock and data connect i.e. do they share the same cable or use different coax cables. (7) Expect major problems of an almost show-stopping level) if expecting to receive data back from the slave. \$\endgroup\$
    – Andy aka
    Jun 30, 2023 at 10:08
  • \$\begingroup\$ 7/0.025 means 7 strands of 0.025mm-dia wires. 7000 MAX indicates the maximum DC resistance in Ohms per km at, generally, 20°C. As for your question, first, forget about an SPI application with 2m cables; and second, google "source-impedance termination" or "source termination" or "source matching". Although they apply to "unterminated" transmission lines, the research will help you find the answer. Oh, BTW, for properly terminated transmission lines, any series resistance such as source output impedance may make things worse. \$\endgroup\$ Jun 30, 2023 at 10:19
  • \$\begingroup\$ @Andyaka (1) I am not completely familiar with all of LTspice's tools, but I will take a look to that. (6) All signals are driven through the same 7-strand cable (thanks RohatKılıç for clarifying those points). (7) I expected these problems, and indeed manifested in a prototype I made. \$\endgroup\$ Jun 30, 2023 at 12:11

2 Answers 2

1
\$\begingroup\$

No, the output impedance does not really need to match the cable characteristic impedance, but if it does, then any reflections from the receiving end will not reflect back. It's usually more important to terminate the receiving end of the cable correctly, so that there will be no reflections back to source to begin with.

That said, any series resistance between output and cable will help as it limits slew rate and bandwidth, even as first order approximation of cable having capacitance.

But, if you are simply connecting an SPI bus between FPGA and another chip by just using logic levels over a 2 meter cable and some series resistors, generally that may not be a good idea as it's not that simple.

SPI bus is generally not intended for extending it via long cables, but for very short communications on same PCB or at most inside PCBs inside same casing.

Depends of course what is the exact cable type, what is the communication speed, and how much noise and reflections the chips can handle - expect poor performance unless the chips have built-in hysteresis or at least decent bus drivers.

SPI is not a "link" that can directly be extended for 2 meters.

\$\endgroup\$
7
  • \$\begingroup\$ There's nothing special about SPI - it can be extended as long as you need provided timings and signal integrity requirements are met. It is very common to not terminate the receiving end, leaving it open and just series terminate the the driving end. Some standard buses such as compact PCI do that. \$\endgroup\$ Jun 30, 2023 at 10:23
  • \$\begingroup\$ @KevinWhite that's not true. If the slave is expected to respond, it is synced to the clock it receives and that clock is already delayed from the master by the cable thus, when the master gets the slave response, it is doubly delayed to the clock it is sending out and, you rapidly reach a point when things are not received in sync. \$\endgroup\$
    – Andy aka
    Jun 30, 2023 at 10:35
  • \$\begingroup\$ @KevinWhitee Sure you can extend SPI as you wish. But just slabbing a 2 meter cable between 2 chips and expecting it to work isn't the correct metod for that. For same reasons you rarely use CMOS or TTL levels directly for any communication protocols when distance is 2 meters. \$\endgroup\$
    – Justme
    Jun 30, 2023 at 14:27
  • \$\begingroup\$ @Andyaka - precisely. That's what I said - it has to meet timing requirements, including any round trip delays. But within those constraints you could run it as far as you need. \$\endgroup\$ Jun 30, 2023 at 14:27
  • \$\begingroup\$ But there is something special (and limiting) about SPI compared to other transmission systems. Other systems can launch data and, fully expect it to be accurately received at many metres distant but, this cannot happen with an SPI slave launching it's data; you are constrained by the sync delays. \$\endgroup\$
    – Andy aka
    Jun 30, 2023 at 14:34
1
\$\begingroup\$

The output impedance essentially does two things: It slows down the edge rate of the transmitted signal. And it presents an impedance for incoming waves. The incoming wave might just be the transmitted wave two transit times later, because of a reflection at the end of the cable.

Usually the first approach is to slow down the edge rates enough, so you can completely disregard any transmission line effects. The actual value necessary to achieve that has nothing to do with the cable impedance (at least not directly). So it may very well be the case that a 100 Ohm (or even bigger) source resistance into a 50 Ohm transmission line will do that for you and solve your problems.

Sometimes you don't get away with slowing down your edge rates, because your link will stop working. In this case you have to choose a termination scheme so your signal integrity is not jeopardized. If your termination scheme of choice is "source termination", then you indeed need a source impedance that matches the impedance of the transmission medium.

If you are simulating this stuff in order to get a better understanding of transmission line effects, I would also suggest to use the "tline" circuit element of LTspice. The tline circuit element adds the one fundamental difference of transmission lines compared to lumped element RLC circuits: Time Delay.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.