# Clock Signal in Finite State Machines

I got this circuit from the book Introduction to Logic Circuits & Logic Design with Verilog, Second Edition. It's on page 248 for reference.

It is supposed to be a circuit that opens or closes a window (I assume a car window).

The Open-CW output is supposed to represent a signal sent to a motor that turns it clockwise, while the Close-CCW signal turns the motor counter-clockwise.

The input Press represents if the button is being pressed.

When thinking about the behavior of the circuit, it occurred to me that if the button was held in the ON state, the output would toggle back and forth from Open-CW to Close-CCW, in sync with the Clock.

I built the circuit, as seen in the picture, and sure enough, that's what happens.

That sort of behavior doesn't really make sense to me. Why would you want your motor to toggle directions with the Clock? I think of clock signals as being automated inputs that have fixed frequencies, generally with many cycles per second. Again, why would you want your window motor to change directions that frequently?

Then it occurred to me, maybe I'm thinking about the Clock incorrectly. In this example, would it be appropriate to use some sort of lever switch located at the top of the window as a "Clock" signal. So that when the window rises fully, it engages the switch and triggers a positive edge and changes the motor direction? Similarly, place another at the bottom so that when the window is down fully, it triggers another positive clock edge and changes the motor direction again.

This functionality would make more sense to me, but is it common and/or proper to use an external input like a lever switch to act as a Clock signal? Am I misunderstanding something fundamental about clock signals?

• Maybe that's just a bad example? As you said yourself, and knowing how car windows work when operated with buttons, it would not make sense to toggle the direction with the clock while button is held down. Jul 1, 2023 at 22:31
• Well if this is a bad example, what are some proper use cases for FSMs? Jul 1, 2023 at 23:22
• the AND gate on the right could be eliminated and the Open-CW term obtained at the output of the top left AND gate Jul 2, 2023 at 0:50