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First thing first, I found a question very similar to this one, so if the answer is already in that one please write it down and I will look there.
While studying CAN bus, I read the distinction between Non Return to Zero (NRZ) and Return to Zero (RZ) ... I would like to trivially ask why RZ, having more transitions, takes up more bandwidth. What is the concept behind this.
Thanks!
That's because for an NRZ signal the fastest signal you can have on wire is an alternating ...101010... pattern which are the bits themselves. For a 1 Mbps data rate the maximum frequency of the square wave is 0.5 MHz.
With RZ line code, for each bit, you have two transitions, which means for 1 Mbps data rate you have 1 MHz square wave.
And, 1 MHz square wave takes double the bandwidth than 0.5 MHz square wave.
10 = 2 bits. So at 1 Mbps that's 1,000,000/2 = 500,000 full cycles per second.
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When you send data on a medium, on top of the data itself, you need to also add some sync information.
Imagine you have a very simple encoding where 1 is a high signal and 0 is a low signal.
If you want to send data which consists of 100 ones, 10 zeroes and 100 more ones, you would end up with a signal that is high for 100 samples, low for 10, and high for 100.
But how can you be sure that the receiver has the same timing as the sender? Maybe its clock is a bit faster than the sender and it will think it has received 110 ones, 11 zeroes and 110 more ones. Or on the contrary it may be a bit slower and it will think the signal is 90 ones, 9 zeroes, and 90 more ones.
That’s why encodings also carry some form of sync information. In async protocols, you usually have start and stop bits, and a small enough number of bits between them that it’s very unlikely sync will be lost between them.
In sync protocols, you don’t have that: you have a long stream of bits (often hundreds, thousands, or even a never-ending stream), and you need to maintain sync.
Some interfaces will simply send the clock on a separate line. That’s the case of I2C for instance: there’s a clock (SCL) and a data line (SDA). The receiver watches the clock, and samples the data line whenever the clock goes from low to high. Everybody stays in sync.
Other interfaces just can’t afford two separate lines for clock and data. So the clock will be somehow embedded in the signal, which carries both data and sync.
In NRZ, you only send data. There’s one state for 1, another state for 0, and while there may be another state for “no data”, it is not used during a transmission. If you send a signal at 100 Mbits/s, and that signal is a succession of ones and zeroes in alternance, then a full cycle (a period) is the duration of two bits. In other words, the same signal repeats again and again every two bits. This gives us a frequency of 50 MHz, and since this is the maximum frequency the signal could have, that’s its bandwidth.
But that signal does not carry any clock or sync information. If you actually have only an alternance of ones and zeroes, as describe above, then it’s easy for the receiver to resync on each transition (from 0 to 1 or 1 to 0), but if there are long series of ones or long series or zeroes, sync could be lost, and the receiver could have counted more or less bits that were sent.
That’s why other encoding schemes try to somehow include sync information in the signal, in addition to the data. In RZ, you have three states, often positive, negative and 0. To send a one, you send a positive signal, then 0. To send a zero, you send a negative signal, then 0.
This allows the receiver to keep sync: whatever the data sent, each bit will start with a transition (from 0 to positive or from zero to negative), and end with another one (back to 0).
But that means that if you have a long stream of ones to send, then the signal you will send will include, for each bit, a transition from 0 to positive and one from positive to negative.
This means that in this case, the signal will repeat for every bit, and the bandwidth in Hz will be the same value as the bit rate in bits/s. So our earlier 100 Mbits/s stream now needs a bandwidth of 100 MHz.
Other forms of encodings like Manchester have the same types of properties. While they only use two states, they will like RZ have up to two transitions per bit. One is for the data, the other is for the clock.
Other schemes are more subtle: instead of sending a clock with every single bit, they send a stream which is mostly one signal per bit, but have rules preventing long strings of ones (or zeroes), so they have lower bandwidth requirements.
