'Best' topology to measure this weird sensor standard

Question

I am developing an embedded solution to measure and record the analog signal from a PCB Piezotronics pressure sensor. Specifically the Model 124A21.

The sensor has some integrated circuitry to boost the signal. My understanding is you need to drive the sensor with a 2mA constant current source, and then the sensor will drive the voltage as the signal.

The common mode voltage of the signal is ~10V, and the swing can be +-5V (the datasheet mentions up to 7V swing, but it's heavily non-linear outside of 5).

I care about the frequency content between 0.5 Hz and ~15 kHz (sensor natural frequency).

My plan so far is to use a 16 bit ADC that has 30-50+ KSPS, which leaves SAR adcs as the best bet. I was also thinking of 100kSPS to leave additional room for additional digital and analog filtering to keep the 15 kHz signal intact.

My main question is now, how do I get this weird 10+-5V signal into either a differential signal or a 0-5V signal? Considering the datasheet seems rather uncertain about the Vcm.

The diagram below shows the sensor on the left with its cable in the middle and the constant current source on the right. The signal conditioning guide mentions the decoupling capacitor generally has values around 30uF, which means a 1 Ohm impedance at 5kHz.

Ideally, I would like a DC-coupled system, which has other benefits, like detecting if the sensor fails.

EDIT: Okay so I think what I want to achieve here is take this 5-15V signal, shift its bias to 2.5V and scale it from +-5 to +-2.5. So that the final signal is a 0-5V signal.

To do this I need to

1. Get a reference of the Vcm using a heavy low pass filter.
2. Us an op amp between the Vcm ref and the true signal. On this opamp I can do my scaling. I reference the output of this opamp to a 2.5V reference.

Maybe do some active low pass filtering with the op amps while I'm at it :)

The datasheet for the sensor can be found here

The manufacturer's signal conditioning guide can be found here

Answer 1

The decoupling capacitor shown in the schematic will block DC. The "signal" out of this would be 0 VDC with AC +/-7V max swing. Assuming a high-quality capacitor.

One could bias this "signal" side of the cap between the power rails of the system. At 5Vdd, using a 1k to signal and 1k to ground would make a 2.5V DC offset.

Then just the AC swing is too large; could use a resistive voltage-divider or opamp to buffer/condition that. Whenever an external signal goes into a chip, good idea to protect that input from over-voltage such as 7 V if the chip can only handle 6.00 V max. Can find many ways to protect inputs here.

If uninterested in amplitude, could use a comparator instead, then even tiny signals (noise also, careful) would appear as full-loudness. There are many details to opamps/comparators so if going that route, plan on research and experiments.

To detect if the sensor has failed requires more information. What are its failure modes? Does it use more, same, or less current when it fails? Does it oscillate or not output any signal? Use the failure modes to determine how "fail" should be detected. Might be the case of "zero change over 1000 samples = sensor must have failed."

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Addition, \$X_C = \dfrac{1}{2 \pi f C}\$. The AC impedance (resistance) of the capacitor is directly related to the frequency of interest and value of capacitance. Two 1kΩ after it forming a 2.5V bias appears in parallel (since the supply rails cannot vary so are seen as immutable) as \$\dfrac{1}{\frac{1}{1k}+\frac{1}{1k}}\$ = 500Ω load. To match this such that 50% signal passes through this cap at 20Hz (Xc = 500Ω, load = 500Ω), rearrange from \$500Ω = \dfrac{1}{2 \pi 20Hz C}\$ to \$C = \dfrac{1}{2 \pi f X_C} \approx 16\$µF. Keep in mind the bias resistor values can be increased if needed; increasing those reduces the parallel load on the capacitor, allowing its value (or the frequency) to be smaller for the same signal throughput. It also becomes more sensitive to noise and external influence.

Answer 2

There’s a number of ways you could approach the problem. The first that comes to mind is you scale the 0..15V value to 0..5V and feed that into your adc. You would then write code to remove the 10V offset to recover the signal of interest. Integrating the adc value with a long time constant would yield the offset value. Subtract this value from the adc value to remove the bias. You could do much the same in the analog domain with a RC filter and op-amp.

Answer 3

Thanks for all the comments. My use case is fairly scientific so I want to do my best to do this as correctly as possible.

The schematic I came up with consists of first scaling the 10+-7V signal to a 10V+-2.5V signal. After that, I shift the signal from a 10V bias to a 2.5V bias.

We need to put a heavy low-pass filter on the input signal to know what value to scale around and how much to shift. This determines the unknown sensor bias of roughly 10V.

We also find the midpoint of the ADC voltage range and use that to determine the required voltage shift. Finally, this is combined with another voltage subtractor to drive the final ADC line with a 2.5V+-2.5V signal.

^{simulate this circuit – Schematic created using CircuitLab}