A simple model for a leaking capacitor is to consider an ideal capacitor in parallel with a leakage resistor, as bellow :
simulate this circuit – Schematic created using CircuitLab
Based on this assumption, in steady state (ie DC), the ideal capacitors behave like open circuits, and we just have a voltage divider based on R1 and R2, and therefore Vout = Vin * R1/(R1+R2)
So the final voltage depends only on the leakage resistors of each capacitor.
So to answer your questions :
- Yes, leakage current (or resistance) will afect the final voltage seen by each capacitor (U_C1 = Vin * R1/(R1+R2) ; U_C2 = Vin * R2/(R1+R2) )
- No, you will not have one capacitor with nearly all the voltage, excepted if they have a completely different leakage resistance. Expect a relative difference in the same order of magnitude than the relative difference in leakage resistance (which might be tightly specified, loosely specified, or not specified at all)
- Indeed, the capacitance of each capacitor will not mater for the final voltage (but will during transients). It might have some indirect influence : for a given manufacturing process, the leakage resistance will vary with the capacity, usually in inverse proportion (higher capacitance = bigger area or thinner insulation layer).
If you care about keeping the same voltage on each capacitor (for example because otherwise you exceed the maximal voltage ratings), then just add yourself resistors in parallel to the capacitors (with smaller values than the leakage), so it is your voltage divider that will fix the voltage on each capacitor in steady state (nb : it will increase the global leakage, so make sure to use low leakage capacitors, so you can use resistors with high resistivity)