My textbook gives the following circuit:


simulate this circuit – Schematic created using CircuitLab

Where both registers are positive-edge triggered D-Type flip-flops.

It describes a how a race can occur when there is a clock skew between A and B such that the output of A appears at the input of B before B sees the rising clock edge.

The problem is that it then says:

To avoid incorrect operation, the clock period is increased to allow for the maximum clock skew. With this constraint on the clock period, the two clocks can also arrive in the opposite order, with the second clock arriving t_skew seconds earlier and the circuit will work correctly.

Why does increasing the period of the clock signal avoid a race here?

To me it seems like a longer period should have no impact at all - the delay between CA and CB is fixed and how long there is between rising edges shouldn't change the fact that A will see any given edge t_skew seconds before B or that the delay between the edge appearing at CA and QA changing is less than t_skew.


2 Answers 2


There’s two issues in play here.

  • Setup time, which is fixable by increasing the period.
  • Hold time, which is fixable by adding helpful skew to Qa clock (that is, route clock to Qb first, then Qa.)

What the text means isn’t so clear. You’re absolutely correct that increasing the period won’t fix hold time. Maybe the text conflated setup and hold?


In your case, CB is slower than CA. You need to add a delay to the signal between RegA and RegB, which can accommodate the clock skew effect. Since an extra delay is added to signal path, the clock period gets increased.


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