I have studied the I2C and SPI communication protocols, but one thing has been confusing for me. In the case of the SPI we have shift registers at both ends and with the help of the SPI rising clock edge the data shifts from the master to the slave. In the case of I2C, I have seen that the values are only transferred if the clock is high. The first question is that if the first value is shifted and we still have a high voltage, then the second bit can also be shifted in the same clock cycle. Secondly, in i2C, it means we do not have a clock on the edges and hence shift registers are not activated on the edges therefore the same problem can occur on the receiver end. The receiver buffer continues to take the two or many values if the clock is high?? Kindly help me clarify this confusion.
3 Answers
When receiving, data is typically clocked in on a clock edge. This is because its convenient and the specs say the data is stable at that point. In controllers with SPI peripheral you can usually adjust when data is clocked in using some control register bit called CPOL and CPHA.
Bellow an excerpt from the datasheet of a nordic semiconductor IC:
You can see that the data is stable for some short time after a clock change.
In I2C it is the same. Here a snippet of the I2C spec from NXP:
You can see that the data USDA must be stable when the clock line USCL changes. You can pick any clock edge to trigger the data shift. Or (in this case) even randomly choose some point between the clock flanks to sample the data. Typically you will want to sample on the rising edge of the clock because some implementations will not honor the falling timings. Have a look at the timing diagram bellow:
The key parameters are Data set up time (tSU;DAT) and Data valid time (tVD;DAT)
Sources:
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In I2C, the "high" states are reached through a pull-up resistor, these aren't actively driven. As such, the rising edges are fairly round, and the exact timing of the edge detector is not entirely well-defined.
So, each bit is transferred at a rising edge of the clock, and the clock needs to be pulled low between bits.
If the data line changes while the clock is high, that is either a start or a stop condition.
With I2C, each clock pulse sends one bit just like with SPI. No difference there.
The data wire is updated by transmitter while clock is low and kept stable while clock is high.
An I2C device loads the data bit in from bus on the rising edge and on falling edge an I2C device sets the data bit to bus.
