# Why would an intermediate voltage level cause a metastability in a SR-latch

Transistors and logic gates are actually analog in nature they aren't digital they don't turn on or off at certain voltages.

In digital logic circuits, a digital signal is required to be within certain voltage or current limits to represent a '0' or '1' logic level for correct circuit operation; if the signal is within a forbidden intermediate range it may cause faulty behavior in logic gates the signal is applied to.

My question is why would an intermediate level cause a metastability if it is still above or below the threshold voltage (is it noise)?

Edit: Sorry I actually didn't specify what I meant by threshold voltage in last paragraph , I meant the threshold voltage of the transistors of the logical gates forming the latch or the flip flop which is the minimum voltage between gate and source where a conducting path is created.

• In your example 0V to 1.5V = 0. 1.5 to 3.5V = unknown. It might be 0, might be 1, or might be "?". Worse yet the undefined level might cause oscillation. So it is 0 and 1 and unknown levels all mixed together.
– user338146
Commented Jul 12, 2023 at 14:41
• The first sentence of your post is the answer to your question. Commented Jul 12, 2023 at 14:53
• In your picture "intermediate" is the space between the orange boxes, not the orange boxes themselves. Commented Jul 12, 2023 at 14:59
• "The threshold voltage" -- it is an error to use the definite article here. The threshold is not a single voltage value that cleanly divides the domain. Commented Jul 12, 2023 at 15:09
• John greg - Hi, Please remember the site rule which requires that when a post includes content (e.g. text, image, photo etc.) copied or adapted from elsewhere, the post's author must correctly reference that content. As a minimum, the source webpage or PDF etc. should be linked. I saw you did that (with correct blockquote) for the Wikipedia content, thanks! To help, I found what I think is the image source & added it. Please remember image references in future too :) || The main site rules are in the tour & help center. Thanks. (You can edit the link I added if it's wrong.) Commented Jul 12, 2023 at 16:24

My question is why would an intermediate level cause a metastability if it is still above or below the threshold voltage?

Transistors and logic gates are actually analog in nature they aren't digital they don't turn on or off at certain voltages.

Real logic gates are made out of logic gates and transistors. These are not digital devices. We only try to arrange them in a way that they operate as much like digital devices as we can manage, but they still aren't ideal digital devices.

To make a circuit with memory (a flip-flop or latch) we design the circuit with positive feedback. That means when the output is not at a valid logic level but only slightly above or below threshold the feedback will push it further away from the threshold level and toward one of the valid logic levels. But there is always a region around the threshold level where the feedback "doesn't know" which way to drive the output, and when that happens we have metastability.

It's analogous to placing a ball near the peak of a hill and knowing it will eventually roll to one side of the hill or the other. If we put it too close to the peak, no matter how sharp we make the peak there is always a region where the ball "can't decide" which way to roll.

(is it noise)?

Noise is not the cause of metastability. Noise is what (eventually) gets the circuit out of metastability and returns it to a proper digital state.

My question is why would an intermediate level cause a metastability if it is still above or below the threshold voltage (is it noise)?

Nothing in your quote is saying or implying this this. In fact, it is specifically implied from the quote that anything in the intermediate range is mutually exclusive from the valid range above or below the voltage thresholds.

The minimum voltage limits for logic HI and maximum voltage limits for logic LO are defined far enough apart so this doesn't happen. So by definition you cannot have an intermediate voltage that is also above or below the threshold voltage.

With regards to the mention about current limits, you need enough current to actually drive the transistor gate-source capacitances fast enough to transition between aformentioned voltage thresholds (to meet timing limits).

If by metastability you mean oscillations, I don't know about logic circuits without memory (feedback) but for logic circuits with feedback consider how amplifiers can oscillate.

If by metastability you mean failing to meet timing requirements, it is not difficult to see how transitions happen more slowly with drive voltages too close to the middle of the range.

Also, if you only use a single threshold to bissect the voltage range (no undefined third zone) it would make it possible to get the wrong output because you got too close to insufficiently precise thresholds due to variances in real transistors. That's why things are defined, and used, with a voltage gap of undefined logic state between logic HI and logic LO.

• Sorry I didn't actually clarify what I meant with threshold voltage I meant the threshold voltage of the transistor which is the minimum voltage required between gate and source to create a conducting path between source and drain. It lies in the undefined range between logical high and logical low. So my question was why would an intermediate voltage cause a metastability even if that intermediate level was still higher than threshold (which would mean that the transistor would turn on and conduct )but still isn't in the range where it is defined as logical high Commented Jul 12, 2023 at 15:52
• I totally understand the second part of your answer though Commented Jul 12, 2023 at 15:58
• @Johngreg Then it is the last paragraph that mainly applies. Also, just barely conducting means low currents and slow transitions failing to meet timing requirements. Commented Jul 12, 2023 at 16:26

why would an intermediate level cause a metastability if it is still above or below the threshold voltage (is it noise)?

You're right to think of digital inputs and outputs as analog in nature (everything is subject to the "real" analog domain.) Its just that "digital" implies strict limitations to what those signals may be.

So a digital buffer is really a high-gain analog amplifier, except that it has been optimized to function "at the rails" and nowhere in-between.

If a 5V input is considered no-go between 1.5V and 3.5V, but "transitions" at 2.5V, the entire 1.5V-3.5V range must be avoided during operation. This is because more parts of the input circuitry are active within that range.

When an out-of-range signal enters a digital input, that input will draw more current than normal (sometimes much more.) Normally any input crosses this level very quickly, so does not present a problem - the bypass capacitors located next to these chips happily provide that brief pulse of current during a normal transition.

But if that transition is slowed or static, this will cause a slight supply voltage reduction due to the large current flowing. This reduction, if delayed and propagated by whatever circuitry is feeding the input, can cause one or more delayed (or a chain-reaction; oscillation) of pulses to occur. Remember the input is high-gain; a tiny signal change at the input can fully swing the output. This could happen very quickly (MHz or ns), which can spell trouble for that device (up to its destruction) and upset the operation of all proceeding devices.

These devices are guaranteed to NOT do this as long as the inputs are kept out of the no-go range and crossings are sufficiently fast. Those parameters vary by logic family but may also vary by manufacturer, so always reference the datasheets of the exact chips being considered when possible.

• Second to the last paragraph is seriously overcomplicating things. The device is destroyed by the heat generated when the large current flows for more than the tiniest interval. Commented Jul 12, 2023 at 15:12

Metastability is something like a broomstick balanced on end. If there isn't much breeze it might sit there for quite a while before it decides to fall one way or the other. It's in a kind of equilibrium, but it's not a stable equilibrium. On the other hand if it's at a 45° angle it will fall one way or the other in a much more predictable manner.

If you feed a signal to one side of an R-S latch that is supposed to change the state but the signal is close to the (voltage and time) threshold of what will change the state, it might sit in a metastable state for a very long and unpredictable time in terms of normal nanosecond propagation delays. And after that it might eventually actually change or it might go back to the original state.

During transitions from L to H and H to L the signal is in intermediate level. Gain of logic is not infinitive to go straight to opposite level.
Also it take some time to cross between states.