I'm trying to learn how to use the 'include thing properly. I had this basic code that works fine to run some 7 segment displays.

module TopLevel(
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2
);
assign LEDR[9:0] = SW[9:0];
function [6:0] HEXER;
input [3:0] IN;
reg A;
reg B;
reg C;
reg D;
begin
A=IN[3];
B=IN[2];
C=IN[1];
D=IN[0];
HEXER[0]=!(A&&!B&&!C||!A&&B&&D||A&&!D||!A&&C||B&&C||!B&&!D);
HEXER[1]=!(!A&&!C&&!D||!A&&C&&D||A&&!C&&D||!B&&!C||!B&&!D);
HEXER[2]=!(!A&&!C||!A&&D||!C&&D||!A&&B||A&&!B);
HEXER[3]=!(!A&&!B&&!D||!B&&C&&D||B&&!C&&D||B&&C&&!D||A&&!C);
HEXER[4]=!(!B&&!D||C&&!D||A&&C||A&&B);
HEXER[5]=!(!A&&B&&!C||!C&&!D||B&&!D||A&&!B||A&&C);
HEXER[6]=!(!A&&B&&!C||!B&&C||C&&!D||A&&!B||A&&D);
end
endfunction
assign HEX0 = HEXER(SW[3:0]);
assign HEX1 = HEXER(SW[7:4]);
assign HEX2 = HEXER(SW[9:8]);
endmodule


And I was under the impression that include "filename.v" would just effectively stick that file's contents into the code as if it was written there.

However the code

module TopLevel(
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2
);
include "HEXER.sv"

assign LEDR[9:0] = SW[9:0];

assign HEX0 = HEXER(SW[3:0]);
assign HEX1 = HEXER(SW[7:4]);
assign HEX2 = HEXER(SW[9:8]);

endmodule


With Hexer.sv being

function [6:0] HEXER;
input [3:0] IN;
reg A;
reg B;
reg C;
reg D;
begin
A=IN[3];
B=IN[2];
C=IN[1];
D=IN[0];
HEXER[0]=!(A&&!B&&!C||!A&&B&&D||A&&!D||!A&&C||B&&C||!B&&!D);
HEXER[1]=!(!A&&!C&&!D||!A&&C&&D||A&&!C&&D||!B&&!C||!B&&!D);
HEXER[2]=!(!A&&!C||!A&&D||!C&&D||!A&&B||A&&!B);
HEXER[3]=!(!A&&!B&&!D||!B&&C&&D||B&&!C&&D||B&&C&&!D||A&&!C);
HEXER[4]=!(!B&&!D||C&&!D||A&&C||A&&B);
HEXER[5]=!(!A&&B&&!C||!C&&!D||B&&!D||A&&!B||A&&C);
HEXER[6]=!(!A&&B&&!C||!B&&C||C&&!D||A&&!B||A&&D);
end
endfunction


refused to compile properly. first it refused to compile when it was just Hexer.v claiming that "declaring global variables was a system verilog feature", and when I made it sv instead of just v it claims. "Can't resolve instance of object "HEXER""

So obviously include is NOT just copy pasting the code over. What is actually wrong here?

I'm using Quartus, and its just a one button that says "Start Compilation", so I'm not sure what else to add. Whatever the Quartus default is I suppose.

This is most likely because the synthesis tools are trying to elaborate the Hexer.v file on it's own, not just the included version. As you are using it as just an include file, you don't want the synthesis tools to elaborate the file.
To combat this, you should instead use the .vh` extenstion - this indicates a "Verilog Header" file, which should lead most synthesis tools to ignore the file itself during elaboration and synthesis.