I am preparing for my exam and I am stuck with this past year question:
In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same timing, i.e. TClk_Q = 0.2ns, Tsetup= 0.5 ns, and Thold = 1 ns. The clock frequency is 100MHz with 50% duty cycle. The clock skew on clock tree network is 0.2ns.
(i) Assume that the worst case delay of the circuit S is 2ns. What is the maximum delay for circuit C?
(ii) Assume that the fastest arrival time of the circuit S is 0.5ns. What is the minimum delay for circuit C?
Any help will be really appreciated. Also some explanation to how your arrived to your answer will be helpful.