Maximum and Minimum delay of combinational logic circuits

I am preparing for my exam and I am stuck with this past year question:

In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same timing, i.e. TClk_Q = 0.2ns, Tsetup= 0.5 ns, and Thold = 1 ns. The clock frequency is 100MHz with 50% duty cycle. The clock skew on clock tree network is 0.2ns. (i) Assume that the worst case delay of the circuit S is 2ns. What is the maximum delay for circuit C?

(ii) Assume that the fastest arrival time of the circuit S is 0.5ns. What is the minimum delay for circuit C?

• Does "fastest arrival time of circuit S" mean the same thing as the minimum delay through circuit S? – Dave Tweed Apr 27 '13 at 15:46
• yes... and can people who down vote the question leave a feedback in the comments? It is helpful to for the poster to understand what was wrong – Saurabh Apr 27 '13 at 16:23
• What answer have you arrived at so far? – Brian Drummond Apr 27 '13 at 16:26
• I am not sure on how to start with this because as per my knowledge, "Hold time is the minimum amount of time the data signal should be held steady after the clock event". But here the hold time is 1ns while the clock is 0.2ns. So to begin with, I am not sure how can i hold the data steady for 1ns when each clock edge arrives after only 0.2ns. Perhaps keep it steady for 5 clock cycles? If i do that then I don't know how to factor that into consideration – Saurabh Apr 27 '13 at 16:58

Let's take this one step at a time. You seem to be confused about the term "clock skew". Clock skew is the amount of time by which the clocks as seen by two different flip-flops can be different.

For example, if you take the clock at FF2 as your reference, the rising edge of the clock at FF3 might occur anywhere from 0.2 ns before the same edge at FF2 to 0.2 ns after that edge.

What this means is that from the "point of view" of FF2, the setup and hold times of FF3 have been "blurred" or expanded by ±0.2 ns, and you now have to think of them as being 0.7 and 1.2 ns worst-case, respectively.

EDIT: So, the maximum delay for C is the clock period (10 ns) minus the quantity (FF3 setup time (0.5 ns) plus the clock skew (0.2 ns) plus the maximum delay for S (2.0 ns) plus the maximum FF2 clock-to-output delay (0.2 ns)), or 10 – (0.5 + 0.2 + 2.0 + 0.2) = 7.1 ns.

Similarly, the minimum delay for C is determined by the hold-time requirement of FF3. You add together the FF3 hold time plus the clock skew, and subtract out the minimum FF2 clock-to-output delay and the minimum delay through S. This works out to (1.0 + 0.2) – (0.2 + 0.5) = 0.5 ns.

• Alright. So is this correct? : The clock period is 10ns. So the max delay for C will be: 10 - (0.2 + 2 + 0.5) = 7.3ns. Now taking clock skew into consideration, the delay will be 7.3+0.2 = 7.5ns. – Saurabh Apr 28 '13 at 17:47
• And for q2 : Min Delay = 0.5- 1 (hold time) = -0.5. And with clock skew it will be : -0.5+ 0.2 = -0.3ns – Saurabh Apr 28 '13 at 17:48
• No, see edit above. – Dave Tweed Apr 28 '13 at 18:29
• so the clock skew gets subtracted in this case? Doesn't skew buy us extra time by delaying the arrival of the clock at FF3? – Saurabh Apr 28 '13 at 19:14
• alright! i get it now! I considered that the skew might help all the time. But I see you mentioned that it might be ±0.2 ns so we have to take the worse case into consideration. – Saurabh Apr 28 '13 at 19:19