For a project, I need to write a binary counter in VHDL that starts at zero, counts to nine, and then resets to start at 0 again.
I wrote the file below, which seems like it should function correctly.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vhdlfilelab is
Port ( clock : in STD_LOGIC;
reset : inout STD_LOGIC
);
end vhdlfilelab;
architecture Behavioral of vhdlfilelab is
signal timer : unsigned(3 downto 0);
begin
process(clock, reset)
if(reset = '0') then timer <= "0000";
elsif(clock'event and clock = '1') then
if (timer = "1010") then
timer <= "0000";
else
timer <= timer + 1;
end if;
end if;
end process;
end Behavioral;
It seems to me that the counter should count to nine, but then be reset by the if statement. Instead, it counts to sixteen before resetting.
Why isn't the counter resetting when it reaches "1010"?
Also, not sure if this is relevant, but my "Force Clock" settings are below.
add_force {/vhdlfilelab/clock} -radix bin {0 0ns} {1 25000ps} -repeat_every 50000ps
add_force {/vhdlfilelab/timer[3]} -radix bin {0 0ns} {1 400000ps} -repeat_every 800000ps
add_force {/vhdlfilelab/timer[2]} -radix bin {0 0ns} {1 200000ps} -repeat_every 400000ps
add_force {/vhdlfilelab/timer[1]} -radix bin {0 0ns} {1 100000ps} -repeat_every 200000ps
add_force {/vhdlfilelab/timer[0]} -radix bin {0 0ns} {1 50000ps} -repeat_every 100000ps
run 800ns
Further testing revealed that the following file produces the same output as the above one.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vhdlfilelab is
Port ( clock : in STD_LOGIC;
reset : inout STD_LOGIC
);
end vhdlfilelab;
architecture Behavioral of vhdlfilelab is
signal timer : unsigned(3 downto 0);
begin
process(clock, reset)
begin
timer <= "0000";
end process;
end Behavioral;
Could the problem be with the force clock settings?