I'm designing a Motherboard with AMD Ryzen 7040 series APU, and I'm interested to use one of it's USBC ports (which support USB 4.0) only as USB 3.2 Gen2 x2 port.

I know that USB-C connector could be connected to two lanes:

Lane 0: (RX1+, RX1-, TX1+, TX1-) Lane 1: (RX2+, RX2-, TX2+, TX2+)

I also know that USB 4.0 supports a dual-lane configuration known as USB 4 Gen 3x2. This configuration allows for a maximum data transfer rate of 20 Gbps per lane, resulting in a total bandwidth of up to 40 Gbps when both lanes are utilized.

In addition, USB4.0 Spec also has the Alt-Mode feature. Outputting USB4 (Gen2, Gen3) or Alt-Mode through the typeC port is decided by the type of device attached and that's followed by communication between the APU and PD controller through I2C.

When a cable is connected, the CC DC-level combination will determine the plug orientation and port role, host or device. Then the host port PD will inquire about cable properties via requests using so-called SOP' and SOP" type VDF (vendor-defined) messages.

I want to know if there is a possible way to use the USB 4.0 port only as USB 3.2 Gen2 x2, where only one lane can work depending on the orientation of USB 3.2 Gen2 devices that are plugged, without the need of PD Controller, and communication of PD-Controller with the APU, and without supporting USB4.0 or Alt-Mode.

Note: this might need BIOS configuration that specifies that the two lanes of the USB4.0 port are separate USB 3.2 Gen2 lanes, where each lane works depending on the current orientation of the plugged device).

Here is an example from the APU symbol, where the lanes are described as lane A and lane B: enter image description here

Is there any passive high-speed multiplexers with plug orientation and power control logic to select whether the SS Tx/Rx in the device go to TxRx1+/- or TxRx2+/-?

This could be a workaround for using highly expensive USB-C PD controllers, and will reduce the price of the BOM. (we already use one USB-C PD controller for the other USB-C ports).

Update: In the past, I used Vialabs VL162, which takes one port of USB 3.2 (TX1+-, RX1+-) and USB2+- connected directly to TypeC port, and outputs 2 lanes of USB for TypeC Connector (TX1+-, RX1+-, TX2+-, RX2+-), and VL162 handles CC negotiations.

but the idea here that I want to use two ports as input, and use them for only one typeC connector.

So I'm thinking about finding a MUX which could take one USB4.0 port from APU (TX1+-, RX1+-, TX2+-, RX2+-, USB2+-), and outputs (TX1+-, RX1+-, USB2+-), or (TX1+-, RX1+-, USB2+-) depending on USB 3.2 device plug-orientation?

This way (TX1+-, RX1+-, TX2+-, RX2+-, USB2+-) could be connected to only one type-c connector, while this way, we only use the usb3.2 capability instead of full USB4.0.

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    \$\begingroup\$ AMD does not support Gen2x2 in Ryzen APUs, there is no corresponding hardware. USB4 cannot be used as USB3.2, it uses different HW encoding. More, you cannot do a thing without full-blown PD. Simply forget your idea and use x670 chip. \$\endgroup\$ Jul 23, 2023 at 18:55
  • \$\begingroup\$ "USB4 cannot be used as USB3.2" - that's true, as long as it's changed in BIOS. since AMD architecture supports multiple protocols on the same signals. \$\endgroup\$ Jul 25, 2023 at 15:30
  • \$\begingroup\$ I didn't say that. You asked for Gen2x2, it is not possible. Yes, Tx/Rx ports are used for variety of protocols, TB3, DP. But to configure the lanes into proper mode you need a PD/CC controller on Type-C port, and communicate the negotiated mode to APU over I2C wires. \$\endgroup\$ Jul 27, 2023 at 1:20

1 Answer 1


Turns out, one workaround could be just using one lane of the USB4.0 ports as (USB 3.2 Gen 2 - 10Gpbs) and leave the second lane as floating. we were able to make this change in BIOS code. This means we can connect TX1+-, RX1+-, USB2+- to Type-A Connector and leave TX2+-, RX2+- not connected.

Second way is using chips. for example, CYAC1126 (USB Type-C Port Controller without USD-PD) + ANX7434 (20G Active Mux (2x2) with Integrated Re-timer and CC Detection for USB 3.2). this can solve the plug orientation issue. but this also means we need to choose in BIOS that the port must be USB 3.2 Gen 2.

  • \$\begingroup\$ So, you did change the topic, and settles for USB3.2 Gen2 x 1 mode. In fact, you don't need any "workarounds" and external MUXes, all MUXes are already incorporated into AMD 's APU. All you need is to properly control the embedded MUXes using I2C interface. And in normal system a dedicated PD chip detects cable properties and plug orientation and retimers, and communicates all this over I2C. But USB3.2 Gen2x2 is still not possible no matter what, period. \$\endgroup\$ Oct 5, 2023 at 4:46

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