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I'd like to use an AVR (ATmega328P-AU to be precise) in combination with a fairly accurate oscillator for timing purposes. I stumbled upon the fact that oscillators which have greater accuracy mostly run on 3.3V or lower and are too fast for an AVR at the same time (>20 MHz).

Luckily I found an 12.8 MHz oscillator available for soldering at my go-to PCB fab. It's even in stock, yay. Problem: It runs at 3V, thus won't deliver suitable HIGH levels for clocking my AVR.

A quick research turned out that many people use the 74AHCT family to convert from 3V to 5V. For example the SN74AHCT1G04DCKR is quite cheap and seems to be idiot-proof as it simply inverts the clock. Now, I'd like to connect the 3V output of the oscillator to the input of the inverter and power the inverter with 5V. Datasheet says that high will be recognized above 2V so this should work. The output will then be connected with XTAL1. The datasheet of the inverter states a maximum rise/fall time of 8 ns, so this should be sufficient for running at 12.8 MHz.

Am I missing a detail or should this work?

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    \$\begingroup\$ What aspects of oscillator accuracy are you most concerned about? Steady-state frequency error? Phase noise/jitter? Duty cycle? \$\endgroup\$
    – nanofarad
    Jul 17, 2023 at 17:43
  • \$\begingroup\$ It's mostly about the timing accuracy over a longer period of time, so I guess it's steady-state frequency error. As long as the long-term timing is fairly accurate I'm good. The oscillator has +/-2,5 ppm accuracy by default. The AVR should be able to handle the output of the inverter, but I don't see any reasons why it shouldn't work. However I'm not an expert regarding oscillators thus my question. \$\endgroup\$
    – Korbinian
    Jul 17, 2023 at 17:54
  • \$\begingroup\$ Is the AVR the only thing using the oscillator output? \$\endgroup\$
    – Ste Kulov
    Jul 17, 2023 at 19:42
  • \$\begingroup\$ The AVR will be the only thing, yes. \$\endgroup\$
    – Korbinian
    Jul 17, 2023 at 20:25

2 Answers 2

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There are no timing problems with this inverter, and its output indeed is compatible with the AVR's inputs. You do not need to invert the signal, so you could replace the '04 with the '125.

  • If the oscillator outputs a 3.3 V logic signal, then the inverter will understand it.
  • If the oscillator outputs a (clipped) sine wave, then the edges might be so slow that you need to use a device with Schmitt-trigger input ('14 or '17). (But that would happen only at frequencies lower than 12.8 MHz.)
  • If the oscillator outputs a signal whose peaks do not go beyond VIL and VIH, then you cannot use a logic gate and must use a comparator instead.
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  • \$\begingroup\$ Thank you for the hint with the clipped sine wave. It's indeed a clipped sine wave, so I guess I'll simply go for a schmitt trigger inverter. Better safe than sorry. This was exactly the kind of 'trap' which I would have headed in head first. Thank you for the suggestion. \$\endgroup\$
    – Korbinian
    Jul 17, 2023 at 20:26
  • \$\begingroup\$ Look at the Δt/Δv specification; you are probably not exceeding it. \$\endgroup\$
    – CL.
    Jul 17, 2023 at 21:43
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Interface might not be required at all.

But let me be particular here: this isn't a production-ready design-grade answer; it's probably too stupid clever for its own good. I would at least urge a statistical sampling process with full voltage and temperature sweep testing to deploy this in production.

But just for hacking together a one-off, it's probably fine.

Anyway, the method.

Consider that the XTAL1/2 pins are (depending on configuration, maybe) the input and output of a single-stage CMOS inverter. (Probably with some bias resistance between them, and maybe other features to control amplitude / bias current / transconductance.)

When such an element is wired to a phase-shift network (like the crystal loaded with capacitors), loop gain has a peak at the resonant frequency, and oscillation results.

schematic

simulate this circuit – Schematic created using CircuitLab

The typical amplitude of such an oscillator is under a volt (in the "low power" configuration). So, clearly a full logic-level signal is not strictly required to get reliable internal clocking. At least as long as the oscillator is free to do its own thing like this.

What we could do, then, is simply capacitor-couple some external signal to the XTAL1 pin, and maybe wire a resistor (say 1M or so) between XTAL1 and XTAL2. (Again, there is probably an internal resistor so this may not be required.)

schematic

simulate this circuit

This should be effective for even fairly weak signals (100s mV?), but several volts should be quite reliable, and rounded (sinusoidal) waveforms should be as effective as square waves. (Just as long as the waveform doesn't have a double-peaked or multiple-zero-crossings sort of shape; a reasonably clean fundamental with at most square-wave-ish levels of harmonics. Which seems to be fine here.)

Notice the active assumptions:

  • Some kind of self-biased transconductance amplifier is present
  • High input impedance
  • Working amplitude as stated
  • Lots of shoulds in here

We can refer to the datasheet to try and check these assumptions:

ATmega328P Datasheet | Microchip

  • Pages 26-28, use of the internal oscillator is discussed. Likely the Low Power configuration would be best suited: internal gain is likely the highest, i.e. most suitable for small external amplitude. (There should be no reason that an "excessive" input amplitude wouldn't work.)

  • Possibly the Full Swing mode would also be suitable. I would guess the XTAL1 input characteristics are similar or identical, and only the XTAL2 output characteristics differ.

  • External Clock mode likely has ordinary logic levels (see below), so would not be suitable for lower input amplitudes. Likely the amplifier bias (or amplification at all) is disabled in this mode, so an external bias resistor would be required for capacitor coupling. It isn't stated whether XTAL2 is active in this mode. (Possibly CLKO could be used for feedback, but an inverter may be required in case it has noninverting phase. It would be limited to 1x prescaler operation.)

  • Page 258, input threshold voltage is given:

ATmega328P page 258, DC characteristics

Evidently, given suitable bias (with AC coupling like so), at least 0.6 VDD peak-to-peak is required. Though that would leave zero noise margin, and a stronger level (say 4V at 5V supply) would be desirable.

  • No other XTAL characteristics are given; p.261 gives external clock parameters but they're only timing.

  • So we don't know actual gain and offset behavior in the oscillator configurations. (Hence, the disclaimer at the top of this post!)

  • Some supporting information appears in AVR186: Best Practices for the PCB Layout of Oscillators | Microchip, but nothing of substance (we do see acknowledgement of the low (~1V) amplitude). I see no other XTAL related appnotes listed in the manufacturer's documentation for this part.

  • Curiously, XTAL pin capacitances are given nowhere, making it difficult to design a crystal oscillator with this family at all(!). It seems they mean their recommendation seriously: the values are strictly "initial guidelines" and a real design should be evaluated for stability and accuracy over temperature and manufacture variation.

Which, curiously, isn't far from the caution this post opens with -- though we can at least hope that intended operation is the more reliable one, and indeed, little trouble is had with using ~20pF crystals with this family. (At least, that I have heard of...)

For confident design purposes, I would, of course, suggest a more canonical solution: use a 5V oscillator, use a buffer/inverter/level shifter (the AHCT part will do fine), or change the MCU's supply to 3V. (It is quite capable at 3V, but if you have other 5V-required devices, and interfacing them would require more level shifters, that's obviously not a suitable option. It is worth mentioning for completeness.)

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  • \$\begingroup\$ One more consideration is start-up time. This processor has fuse selection provision for oscillator stabilization time - I'd suggest that it should be set for maximum. The time constant of that 100pf coupling capacitor with 1MEG(?) internal bias resistor might settle slowly to half-Vdd. However, a small capacitor might allow spurious glitches. \$\endgroup\$
    – glen_geek
    Jul 21, 2023 at 12:49
  • \$\begingroup\$ @glen_geek Yes - startup time should be set based on the RC time constant and the source oscillator's startup time, whichever is longer. \$\endgroup\$ Jul 21, 2023 at 14:56

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