Split or not split the ground plane in a low-noise design?

For low-noise design, many component datasheets suggest dividing the ground plane into AGND and DGND and linking them with a star connection.

But my ten years of experience in EMC have shown me that it's not quite that simple. In fact, the connection between annalog and digital parts create a loop because the analog current has two return paths.

The loop behaves like a coil, and can couple to its environment by mutual inductance. Imagine adding an SPI device in proximity of the loop:

The mutual inductance between the two loops is equal to:

$$\L_m=5.08\cdot\frac{A_1\cdot A_2}{r^{3}}\$$

With

• Lm = Mutual inductance (nH)
• A1 = Area of loop 1, the star grounding (inch²)
• A2 = Area of loop 2, the SPI bus (inch²)
• r = Distance between two loop (inch)

If you known the slew-rate current of the SPI (Δi/Δt in A/s), the voltage noise on the loop1 equal to:

$$\V_{noiseA_1}=L_m\cdot\frac{\Delta I_{SPI}}{\Delta t_{SPI}}\$$

I known three solution for reduce this problem, see illustration below

However, I always thought that EMC testing (IEC 61000) would be problematic with split-grounding, as common-mode currents, radiated or conducted, would cause a loss of equipotentiality of the split grounds. So, in all my designs, I've never divided my ground plane, I've always had a solid ground with a strategic placement of components as in the image below (an example):

And you? How do you manage design with low-noise analog? Is there a good compromise between star ground and solid ground?

• Do you mean "analog" (US) or "analogue" (UK) when you say "analogic"? I don't see the two current return paths as you suggest. Commented Jul 22, 2023 at 13:19
• I don't either. Current from the analog supply flows either to the Agnd connection or to the digital circuit, but not both. It really isn't a "loop" at all, at least not in the way we normally think about ground loops. Also the "loop area" associated with the SPI connection is limited to the spacing between the SPI conductors and the digital ground plane over which they run. Furthermore, this "loop" is at right angles to the analog-digital ground loop you're worried about, further minimizing coupling. Commented Jul 22, 2023 at 14:13
• That said, it is important to think about how signal pass between the two areas. For example, minimize the number of such signals to start with, and physically route them as close as you can to the ground star point to minimize loop area in both domains. Also, pick an interface technology that inherently minimizes ground noise -- e.g., CMOS for low-speed signals, LVDS for high-speed. Commented Jul 22, 2023 at 14:19
• Let's imagine that the analog part is an op-amp and the digital part is a microcontroller with an ADC (for example). The current to the digital part is the operational amplifier's output current (Io), and its return path is DGND. The operational amplifier's quiescent current (Iq) has its return path in AGND. Io and Iq come from the VA power supply current (in my diagram), which splits in two and flows along two different paths. This is a loop. Sorry for the "analog" confusion, I'll try to modify my drawings. Commented Jul 22, 2023 at 16:35
• Try solution 4 there is in addition to solution 1 signal from analog to digital goes with ground conductor. Quiescent current should be taken in account. Commented Jul 22, 2023 at 22:52