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The PCIe Gen 3 standard states that the link works at 8GT/s, while the fundamental frequency of the LVDS signals is maximum 4GHz. To my understanding PCIe doesn't use any sort of DDR technology, so how is it that we get two "transfers" per physical transfer period?

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If you send a data stream consisting of the most transitions possible, that would be alternating bits (1010101010...), you end up with a square wave with a fundamental frequency of half the bit rate.

So for PCIe Gen 3, an 8Gbps bit rate, gives a fundamental of 4GHz. The same would be true for any two-level digital interface.


From an implementation standpoint, the PCIe serial lines are encoded/decoded using SERDES (serialiser-deserialiser) hardware which converts between a parallel data bus and a serial data stream.

Typically such hardware will use some form of PLL to step the reference clock (100MHz for PCIe) up to a frequency high enough to clock the serial interface.

Many of the implementations of these SERDES blocks make use of double-data-rate logic internally to reduce the maximum clock rate needed. They will start by packing the stream from N-bit to a 2-bit word generated each clock cycle. This 2-bit word is then multiplexed using the clock signal, sending one bit while the clock is high and another while low.

It is common for PCIe Gen 3 SERDES hardware to see them using a 4GHz clock internally for this reason, even though the interface is not what one might normally consider "DDR".


As a side note, PCIe uses CML (current-mode logic) not LVDS.

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  • \$\begingroup\$ okay, I suppose I was confusing a sort of separated clock-synchronous interface where data lines are sampled once per clock cycle but instead the data has the ability to change 8G(times) per second, which would result in a 4GHz fundamental. Thanks! \$\endgroup\$ Commented Jul 22, 2023 at 22:27

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