I am trying to implement a 10GBASE-R PCS on an FPGA (Xilinx Kintex UltraScale+ Family). First of all, I understand that the included on-board transceivers provide native 64b/66b gearboxing, so I am mostly implementing this design as a learning opportunity (trying to make an ultra-low-latency design).

I configure the GTY in Raw mode with Buffer Bypass (the lowest latency mode possible) and wait for the Phase/Delay alignment procedure to finish before I start sampling the data and export it for later analysis with software tools. I wrote a simple script to scan the bitstream bit-by-bit, and look for possible offsets at which the sync-header is seen.

The stimulus is generated from a reference network stack implementation by Alex Forencich's Ethernet Stack and I am looking at the RX Userdata from my GTY. My design uses the Example IP generated by Xilinx, with the PRBS checkers replaced by my own simple logic to dump the output values.

Manually looking at the Serial input and Parallel output from the GTY seems to match, however, I always see two different possible offsets where the sync-header could be, always separated by 33 bits. I have tried everything, including double-checking the GTWizard for possible clock-rate errors. Have you seen something like this before, and why do you think this could be happening? Thanks in advance!


1 Answer 1


This has been solved. This is because the data width on the transmitting GTY (stimulus generator) was also set to 32 bits accidentally, so the headers were transmitted after every 32 bits of data instead of 64.


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