First of all, good job!
I'm not an expert in KiCad, but whenever you have such question, you can check the gerbers. They never lie since it's the file your manufacturer will use!
Here are the answer to your questions:
1 Take this via for example. Does the black area between it and the PWR (VIN) plane mean it's isolated from the plane? Else it would be shorted! -> Yes it's isolated from ground.
2.Take this via for example. If the standard trace goes into the filled zone, does that mean it's making contact and they're connected? -> I would say so, but be careful, based on other software (Altium) the behavior when repouring might surround your trace. Here it doesn't seem to be an issue.
If the via is itself isolated, is there any reason to make another isolation copper island like in the photo below? -> Not to my knowledge. I'm not working in very high voltage, but I don't see any reason to place that (except plane filling FYI-> when you have 8+ layer, you must ensure all your plane have copper on so the PCB remain flat)
Is there any reason to use these "thermal reliefs" over standard tracks? (I did it since I heard they're good) -> Thermal relief are very important whenever a huge part of copper is connected to a pad. Either a plane or a trace. Otherwise, it will be very hard to solder since the pad will remain cold. Not having thermal relief can also make component stand up.
Here are some of my comments on your layout
All the rules you have listed are good in general design. So, why did on the bottom layer didn't you place a plane!? (It's large, yes but it can be larger!)
Having huge vias, in general is not as good as several smaller. The impedance of one large via can't match 20 smaller one.
Your power plane (Vin) is highly degraded near the IC. I don't know your clearance constraint but they seem a bit loose which make the plane weaker.
Usually, you would want your stackup for a four layer to be (top to bottom) Components and most traces, GND, PWR, Rest of traces. The reason why this is the best topology is that the most trace are close to the gnd which give them a better impedance control. Also, it increase the capacitance between the GND and supply (this is the best decoupling capacitance since it has a very low ESR). Finally, it allow a way easier debugging since you can cut trace (I once had to cut a trace on a third layer, you don't want that!).
You have some very narrow trace that are quite long. I'd make them a bit wider so they are less lossy.
You seems to have some very small vias. Even if not a lot of power goes tough them, they are harder to manufacture and will increase to a more expensive board and a higher failure rate.
I haven't review the layout. With a quick check, I think your output capacitors are way to far away from your chip, but I'm unsure.
If I had an advice to give you is to get the best PCB design, spend as much time doing and redoing your component placement. That's what makes the difference! And with practice, it will take you less and less placement to have a good and neat PCB.
The image is too pixelized for more comments, but I'm impressed! I have seen worst from actual PCB designers!