I think the easiest way to start thinking about this question is to imagine a "perfect-in-all-other-ways" parallel 8-bit ADC; it produces an 8-bit number every time it converts. It's an 8-bit device so it only approximates to the real analogue input fed to it.
Let's say it's input span is 0 to 2.55V - each lowest bit change is worth 10mV and 10mV is its resolution and accuracy (remember it's perfect in all other ways). If you inputted 1.015V, it would produce a digital output the equivalent of 1.01V i.e. there is an error of 5mV.
Now consider this situation: the ADC output is converted back to analogue by an 8-bit DAC and subtracted from the input voltage to produce an "error" voltage. Consider also that the error voltage is integrated and now feeds into the ADC's input instead of the original input.
What now happens is the the output of the ADC will hunt above and below the precise value of the real input voltage. Several consecutive ADC outputs can now be averaged (in the digital domain) to get a progressively more accurate picture of the real analogue signal.
Why not use a 4-bit ADC? If 4-Bits is used, to achieve the same accuracy as the 8-bit ADC, more consecutive results need to be averaged to accomodate the chunkiness of 4-bits compared to 8-bits.
Take this to extremes - imagine a one-bit ADC - basically it's a comparator - plenty of results need to be taken and averaged to reach the equivalent of an 8-bit ADC but if the speed is high and the processing power is good then no problem.
The difficulty explaining this type of ADC is that if you "use" the the normal Delta-Sigma single-bit architecture, the digital numbers produced can befuddle the mind. Anyway that's my take on things!