While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock. enter image description here

The characteristic of DDR is that it transfers 2 sets of data every cycle. Therefore, for older versions of DDR without prefetch, the calculation of Transfer rate is Memory Clock * 2.

With the advancement of DDR technology, the concept of prefetch emerged. As I understand it, prefetch is a concept related to the DRAM's internal Burst Buffer.

Therefore, I understood it as Burst Length = n prefetch. Is my understanding correct?

And why is the I/O bus clock half of the transfer rate?


1 Answer 1


In an SDR clocked system, the frequency of the clock line will be twice that of the data lines because the data will only change after a rising edge of the clock. If you transmit an alternating pattern of bits, you see

clock   01010101010101010101010101
data    00110011001100110011001100

Because the frequency of the clock is higher, it is more difficult to build a transmission line that can transport it, so the clock rate is deliberately halved for transmission.

Most other applications only use the rising edge because there is no guarantee that the time the clock is read as "high" is exactly 50%, so you can only get a stable clock from looking at either the rising or the falling edges.

DDR memory requires a 50% reference voltage and termination resistors that pull towards that reference voltage to compensate for this, which is also considerable effort to implement.


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