Some time ago I posted a question about weird oscillograms of half-bridge, gate spikes on mosfet openings. After some investigation, it was revealed that the problem is not in transformer leakage inductance. When the upper or lower MOSFET is turning off, a voltage spike appears on the gate of the opposite MOSFET and vice versa. This behavior remains also when replacing transformer with resistor. Surprisingly, that IR2110 LTspice simulation, also draws some gate spikes while opposite mosfet is opening.

Of course, gate spikes amplitude is proportional to the half-bridge rail voltage. Spikes leads to shoot-through.

I guess the problem has something to do with Miller Cdg? The PNP transistors, gate dischargers, connected to the gate doesn't solve the problem even in simulation.

Is it possible to get rid of these spikes, without resorting to transformer-coupled gate drive circuit?

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Oscillogram taken using 10:1 probes

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LTspice simulation files

  • \$\begingroup\$ Unfortunately we don't know the node numbers on your schematic so we don't know what the waveforms represent. There seems to me several problems 1/ the 5R resistor (never seen that before) 2/ the value of the boost capacitor is completely excessive 3/ there is no resistor in series with the boost diode to limit charging current 4/ there is very little decoupling on vcc/vdd Hopefully addressing the above will improve your results. \$\endgroup\$
    – anon
    Commented Jul 31, 2023 at 16:24
  • \$\begingroup\$ Does this answer your question? Half-bridge oscillogram spikes, possible shoot through \$\endgroup\$
    – Andy aka
    Commented Jul 31, 2023 at 17:06
  • \$\begingroup\$ Waveforms represents: (blue waveform) gate-source high side mosfet and (green waveform) gate-source low side mosfet. You can test LTspice simulation, google drive link drive.google.com/drive/folders/… \$\endgroup\$
    – Erch
    Commented Jul 31, 2023 at 20:54

1 Answer 1


The waveform is due, in part, to loop inductance and Cdg.

Modified inverter circuit

If you add loop inductance like so, with typical values say 10nH, you will most likely see similar waveforms in the simulation. (Some combination of drain, source or C6 inductance is most realistic; I'm just showing S here for simplicity.)

Realize that, when a transistor turns on (and its initial Vds is large), it discharges its own capacitance (this has no effect on the surrounding circuit, but dissipates some switching loss), and the capacitance connected around it. Which is in the M1-M2-C6 loop (and now Ls1, Ls2). This makes an LC circuit between the opposite transistor Coss and loop inductance, and this causes common mode overshoot/ringing at the gate signals (which makes probing them problematic, in fact you may find that noise anywhere in the signal depending on how your layout is).

Layout matters, because inductance is geometric, spacial (because magnetic fields are, well, fields; fields fill space). It's in the ballpark of 0.5nH per mm of wire or trace length. Go around the loop and add it all up (includes component body and lead lengths!).

BTW, note that D4 and D2 are superfluous; the MOSFETs have body diodes internally, as shown by the arrow in the middle (the substrate connection pointing towards the channel, making a PN junction). UF4007 would certainly be too small to pair with 20A transistors anyway.

D3 and D5 aren't very useful either, with values as shown; see explanation: https://electronics.stackexchange.com/a/675433/311631


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