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From what I know, if we need to instantiate module1 in module2, then I need to declare all the inputs & outputs of module1 as reg & wire respectively in module2.

But often times, I have seen that even with all input-output ports being declared as reg, the simulation works. Can someone explain what's the correct way of port declaration?

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It is possible to declare all signals in module module2 as reg. However, this is only supported by SystemVerilog (IEEE Std 1800). It is not supported by Verilog (IEEE Std 1364). For example, this syntax is legal in SystemVerilog:

module module1 (input clk, output data);
endmodule

module module2;
    reg clk, data;
    module1 i0 (.clk(clk), .data(data));
endmodule

However, the above is illegal in Verilog. You need to declare the module1 output as wire for Verilog:

module module2;
    reg clk;
    wire data;
    module1 i0 (.clk(clk), .data(data));
endmodule

Using wire is also legal for SystemVerilog.

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  • \$\begingroup\$ Do things change if we define output reg - ie. does Verilog allow a reg output port to be declared as reg? Also what's the difference between declaring a port as wire or reg specifically during instantiation? \$\endgroup\$
    – Killjoy
    Aug 2, 2023 at 11:18
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    \$\begingroup\$ @Killjoy, for a Verilog answer, see my old answer. For SystemVerilog you may have to ask a new question. \$\endgroup\$
    – The Photon
    Aug 2, 2023 at 14:11

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