I'm designing a PLL circuit to stabilize a ~200MHz VCO against temperature-induced frequency drift. However, I need to be able to occasionally (~few times/sec) send a short pulse (~few μs) to modulate the VCO output by <1MHz. The image below (modified from this nice PLL overview) shows how I imagine doing this, by simply adding the modulation pulse to the feedback voltage. However, since the VCO output is not matched to the reference signal during this pulse, I worry that the lock may behave strangely after the pulse ends.

Since the PLL is only intended to protect against slow temperature-induced drifts, would it make sense to simply use a very low cutoff frequency for the loop filter, such that the feedback voltage doesn't have time to react to the pulses? Should I expect other issues with this design?

Extra details about my circuit: the VCO is a Mini-Circuits ROS-244R+. I want to lock to a <25MHz function generator, so I intend to divide the VCO frequency by 16 (using two HMC433 freq/4 ICs). Hopefully the MAX9383 phase-frequency detector works for this design. The loop filter would presumably be a lead/lag filter, and my thought is that a very low cut-off frequency would work, maybe even ~1Hz. Finally, the summation would be done by a fast summing op-amp.

Phase-locked loop with frequency modulation

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    \$\begingroup\$ Provided the modulation is sufficiently higher in frequency than the PLL loop bandwidth and the modulation pulse accumulates a net zero phase, there shouldn't be any issue. Given that you're looking at bandwidths on the order of Hz, this sounds like the case. \$\endgroup\$ Aug 2, 2023 at 17:22
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    \$\begingroup\$ If you use a low bandwidth loop filter, you should also think about the initial acquisition dynamics. Even if you have an integrator in your loop filter (which should give you infinite lock range assuming a perfectly linear system), integral wind-up can result in an inability to achieve lock. There are techniques to fix this issue, involving a frequency "hunting" mode during acquisition, where the tuning signal is swept back and forth until a lock condition is detected. \$\endgroup\$ Aug 2, 2023 at 17:27

1 Answer 1


If you must apply occasional frequency shifts you should do 2 things more

  1. Freeze the PLL phase control during the shift
  2. After the shift let the output continue like there were no shift - you must not cause a phase jump!

In practice you must synchronize the frequency shift to start and stop at the same phase angle.


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