I'm designing a PLL circuit to stabilize a ~200MHz VCO against temperature-induced frequency drift. However, I need to be able to occasionally (~few times/sec) send a short pulse (~few μs) to modulate the VCO output by <1MHz. The image below (modified from this nice PLL overview) shows how I imagine doing this, by simply adding the modulation pulse to the feedback voltage. However, since the VCO output is not matched to the reference signal during this pulse, I worry that the lock may behave strangely after the pulse ends.
Since the PLL is only intended to protect against slow temperature-induced drifts, would it make sense to simply use a very low cutoff frequency for the loop filter, such that the feedback voltage doesn't have time to react to the pulses? Should I expect other issues with this design?
Extra details about my circuit: the VCO is a Mini-Circuits ROS-244R+. I want to lock to a <25MHz function generator, so I intend to divide the VCO frequency by 16 (using two HMC433 freq/4 ICs). Hopefully the MAX9383 phase-frequency detector works for this design. The loop filter would presumably be a lead/lag filter, and my thought is that a very low cut-off frequency would work, maybe even ~1Hz. Finally, the summation would be done by a fast summing op-amp.
