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I'm setting up a hyperram, and I want to run it at 200MHz, with the DHQC setting enabled. The peripheral manual on page 874 says:

DHQC must not be set when the prescaler value is 0, as this action leads to unpredictable behavior.

Therefore, with a minimum prescaler value of 1 (division by 2) the input clock must be 400MHz. I have set this up, and it seems to work fine.

BUT, when I try to enter these values into the cubeMX code configurator, it complains, saying:

DIVR2 output frequency is currently set to 400MHz. Must be <=280MHz.

clock configurator screenshot

I can't find any reference for this limitation in the peripheral manual. Is that true?

I tried setting the PLL output to 200MHz, and setting the prescaler to 0, and that did not work.

Edit: Based on brhans suggestion. I tried switching the OCTOSPI clock mux to a different input, and that eliminates the error. So perhaps the problem is the input frequency to the OCTOSPI peripheral? I can't find a limitation for that either.

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    \$\begingroup\$ Which modules are being clocked by PLL2R in your configuration? It could be one of those other modules which is imposing the limit in CubeMX. \$\endgroup\$
    – brhans
    Commented Aug 3, 2023 at 14:38
  • \$\begingroup\$ Good observation! There is only the OCTOSPI clock mux, but if I change that to use a different input the error goes away. So maybe the problem is the input to the octospi peripheral, question updated. \$\endgroup\$
    – Drew
    Commented Aug 3, 2023 at 14:54
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    \$\begingroup\$ There are a couple of 280MHz limitations shown on Page 360 of the linked manual. Perhaps you've got one of them clocked. \$\endgroup\$ Commented Aug 3, 2023 at 14:58
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    \$\begingroup\$ Datasheet, page 84, says the max allowed clock frequency for the OctoSPI module is 280MHz. \$\endgroup\$
    – brhans
    Commented Aug 3, 2023 at 15:02
  • \$\begingroup\$ @brhans Thanks there's the answer. You'd think that would be in the peripheral manual... If you post that as an answer I'll mark it. \$\endgroup\$
    – Drew
    Commented Aug 3, 2023 at 15:11

2 Answers 2

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This table of Maximum allowed clock frequencies from page 84 of the datasheet says that the maximum clock frequency for your STM32H7A3's OCTOSPI module is 280MHz:
enter image description here
So you cannot run your HyperRAM at its top speed from the MCU.

I've had a similar frustration recently with a STM32H750 where I can't run my SDRAM at its maximum 166MHz because the MCU's FMC module can't support anything higher than 110MHz.

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The maximum clock frequency for the core and some peripherals is 280MHz, found in Table 23 on page 84 of the datasheet:

enter image description here

DIVR2 output frequency is currently set to 400MHz. Must be <=280MHz.

This error message implies that the PLL clock is being set to a frequency higher than will work in the MCU. A standalone PLL may work up to 420 MHz if I am not mistaken, but if integrated into an MCU that cannot support those speeds then the MCU speed dictate the maximums. CubeMx has caught that for you.

This is the clock that supplies an entire clock domain within the MCU and may be pre-scaled as necessary.

The same datasheet in Table 90 on page 140 shows that the maximum clock is less than 280MHz for the SDR mode

enter image description here

And even less in in DTR mode.

enter image description here

This suggests that the maximum Fclk is 140MHz (foctospi_ker_clk/2). Only for the following:

  1. Condition VOS0
  2. VDD>2.7V
  3. Possibly: external power,
  4. Possibly: Internal LDO and buck converter disabled

There may be other conditions that I did not find.

I don't know the HyperRam devices or protocols, but it does appears that 200MHz data rate is not possible. The maximum is 140MHz.

DHQC must not be set when the prescaler value is 0, as this action leads to unpredictable behavior.

This allows a 1/4 clock period delay, so the data clock must be 1/4 the foctospi_ker_clk.

Caveat: I have used STM32 M3 and M4 chips. not any M7. I cannot work through the manual/datasheet in detail in the time that I have.

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