# Need an explanation of how the circuit works

I came across this bidirectional switch circuit by Texas Instruments.

I know how two MOSFETs configuration works but when I apply the pulse to turn it on and off the NMOS but it does not change its state as in the figure:

I know that I'm missing something here but I can't see it. How am I supposed to turn it on and off so it can also turn the back-to-back PMOS on and off?

For information, this switch is for battery application. It is controlled by the charge states of the batteries(overcharge, undercharge) and also overcurrent condition. This NMOS is connected to the output of the circuit breaker so if any faulty condition occurs this switch is opened.

There are several problems.

First is that of the RC load time constant:

100 Ω x 10mF = 1s

The capacitor will discharge by about 10V in one second.

You’re watching it over a time period of <1ms, with poorly scaled graph.

Second problem is that of the RC time constant of the gate RC load.

10 kΩ x 100nF = 1000 μs = 1ms

The switching period you chose is less than this time constant. Have you plotted the gate-source voltages for both mosfets - and you should :) - you’d have noticed that the mosfets never have enough time to turn off.

The switch you’ve built is meant to be “slow”. Try switching it every 0.2s for example. You’ll see it works fine although the switch-off action is “soft”, ie. takes more time than you’d expect due to the gate time constant. Switch-on is quick of course since the gates get hard-shorted to ground.

If at all possible, switches like this can be driven with a push-pull gate driver that can swing the gates between 0V the supply voltage (same as max switched voltage).

The switch circuit shown in the question consists of the switch proper, and a gate driver. These two parts are orthogonal (independent) to an extent, and can be analyzed separately. At the highest level we have a switch controlled by a floating voltage source:

simulate this circuit – Schematic created using CircuitLab

For suitably high switching frequencies (no DC), the following block diagram would also work:

simulate this circuit

More contretely, and keeping in mind that the transformer symbol is a block representation of a floating gate driver:

simulate this circuit

Then, we can see what the gate driver proposed in the question would look like. It's important to note that the parallel gate RC circuit is conceptually a part of the driver, not the switch itself. The switch doesn't need such a circuit, it's the simplicity of the driver that calls for it:

simulate this circuit

SW1 can be an NPN, N-MOS, open-collector or open-drain driver, etc. SW1, R1, R2, C2 are a rather crude gate driver. We can do better though.

It'd be a reasonable assumption that the power supply lines we have available for the gate driver would encompass the potentials at A and B, i.e. $$0 \le V(A) \le V_{CC},\\ 0 \le V(B) \le V_{CC}.$$

Now we can imagine a push-pull driver for the gates:

simulate this circuit

The purpose of R2 now is only to keep the A-B switch turned off when the gate drive is not available, e.g. when VCC is lost.

Next, we can implement a rudimentary push-pull driver that will perform much better than the N-MOS/NPN circuit we started with:

simulate this circuit

Cg1 and Cg2 represent the inherent gate capacitances of the mosfets. Typically, Cg1 will be an order of magnitude smaller (or more!) than Cg2.

It is much less effort (charge transfer, peak current, etc.) to drive M1 and M2 vs. driving the primary switching elements.

simulate this circuit

Now the R3 pull-up only has to charge the relatively small Cg2. The large Cg1 is driven actively by M1 and M2.

If VCC is 18V or less, a 50-year-old (!) complementary driver CD4041 will do well as a driver for M1 and M2:

simulate this circuit

In fact, a CD4041 should have no trouble driving Cg1 directly. Each of the eight outputs in the 4041 can drive ±10mA. Let's assume Cg1 is representative of high-power, large-gate mosfets - say 2nF.

The ramp up/down time for Cg1 is then: $$t = \frac{C_{g1} V_{CC}}{I} = \frac{2{\,\rm nF} \cdot 18{\,\rm V}}{10{\,\rm mA}} = 3.6{\,\mu\rm s}.$$

Paralleling all 4 drivers inside of CD4041 gives a respectable switching time of ≈1μs - for a very low cost, too. This switching time is quite "EMI-friendly". Faster transitions would radiate quite more, make the PCB layout more critical, etc.

simulate this circuit

Using a 4041 has a bonus: if you needed to drive another switch with a control signal complementary to the one you already got, you've already got the complementary gate drive available:

simulate this circuit

AB, CD are connected via alternating switches: when AB is connected, CD is open, and vice-versa. There's a slight overlap in their conduction, so they could form a make-before-break SPDT switch.

• Thank you very much it helped, I should have plotted the VGS :) I corrected the pulse so that it is now longer than the time constant of the RC. But what can I do to shorten the turn-off time of FETs as it takes too long? Aug 4, 2023 at 13:15
• I can put smaller capacitance but what value is optimal? Aug 4, 2023 at 13:22
• @Shamurov There is no globally optimal value. These switches have inherent tradeoff between charge injection into the signal they switch vs. turn-off-time vs. sensitivity to dV/dt on the switched line. Ideally, you'd want to drive the switches from an external push-pull driver - then no capacitor is needed at all, since gates are driven from a low impedance. If your application is just to switch a power line, you can probably remove C16 altogether. The gate capacitance provides enough filtering. The switch has two independent parts: the switch and the driver. The driver you show is very basic. Aug 4, 2023 at 14:05
• @Shamurov It also helps a lot to have the requirements for the circuit you work on specified in the question. If there is a particular slope or switching time you require, this must be included in the question. Otherwise, a true but potentially useless answer could be "your switch works as-is" - but whether it works for your requirements is up in the air so the answers can't be too specific. So that doesn't help you, in fact. Also indicate (edit the question, not comment here) what supply voltages are available for any driver circuit, since you may need a different gate driver. Aug 4, 2023 at 14:07

Compare the time constant of C16 * R54 to your PULSE period. Something is missing here.

• Do I have to set pulse period equal to the time constant? Aug 4, 2023 at 11:50

Another thing to consider is the IRF510's $$\V_{GS(th)}\$$ parameter. This is specified as a maximum of 4V to cause 250µA to flow between drain and source. So 5V might cause 5mA to flow, which greatly slows down the other FET transitions due to the other answers.

If this FET is replaced by a true "logic-level" FET, it should yield much better results.

• Thank you I updated it to 2N7002 Aug 4, 2023 at 12:27

Think about how you can get a voltage across R61. The only voltage source you have the generator on the gate.

Put a voltage at A and look at B.

Then put a voltage at B and look at A.

• Notice there is a capacitor that I put at B. The switch works and the current flows from B to A when I apply a voltage to the gate of the NMOS but it does not turn off. Aug 4, 2023 at 11:07