Problem generating two asymmetrical pulse waves

Question

I am trying to generate two pulse waveforms with a on to off time ratio of around 40/60. The max amplitude is only 5 V however the switching frequency is quite high at around 100 kHz.

The two waveforms should have a phase offset of around 180 degrees, resulting in the on time of one wave lining up exactly between the off time of the other. It is imperative the phase relationship stays the same.

I have designed a quick diagram below to show what I'm aiming for:

I have tried multiple solutions. I am aware a micro can easily do this but I would want a discrete solution if possible.

I have tried the following:

• A 555 timer. This did generate one waveform however I don't know how to generate another waveform that has the correct phase relationship (e.g. two separate 555 timers won't 'line up').

• A astable multivibrator. This is presented the same issue as above.

I would really appreciate any input. This is a fairly complex problem so I'd be interested other what people think. Thank you.

Answer 1

This idea uses five of the six the schmitt-trigger input inverters of a 74HC14 package:

^{simulate this circuit – Schematic created using CircuitLab}

The first gate G1 is a relaxation oscillator running at about 100kHz, producing a roughly square wave at SQ, which is buffered by G2. G2 and G3 outputs are inverted with respect to each other, and used to feed the next stages.

The diode, capacitor and resistor networks produce ramps at the inputs of G4 and G5. The charging path impedance during ramp up is different from ramp down, due to the diode, which pushes the duty cycle away from 50%.

G4 and G5 convert the ramp signals back to digital.

The result is something like this:

The initial delay prior to 10μs is just the oscillator starting up, settling into its rhythm.

These simulated gates have less input hysteresis than real 74HC14 gates, so the resistor values will have to be adjusted to produce the exact frequency and delays you require.

R3 and R6 are marked as variable, because they control the asymmetry of the ramps' rise and fall rate, and will need to be adjusted to obtain the duty cycle you require. You can of course combine R3 and R4 into a single resistance, and R6 and R7 too, once you have determined the required resistances.

The gates must have schmitt trigger inputs for this to work, so don't use a 74HC04. Don't leave any unused gate's input unconnected. Always tie unused inputs high or low.

Answer 2

You need a toggle flip-flop to generate alternating pulses -- this gives you an exact 50% reference -- and then some logic to AND the Q and /Q outputs with the clock. The clock waveform can have a high duty cycle, to implement the dead time. (This is an SMPS application, right? You don't have to hide it.)

Such logic is integrated in push-pull SMPS controllers such as SG3524, TL494 and UC3525. Here is an example:

For which the block diagram is:

^{From SGx524 Regulating Pulse-Width Modulators | TI}

The oscillator's output is low while the capacitor charges (through a current mirrored from the RT pin), and high while it discharges (through an internal switch that draws more current). Thus a low duty cycle is created. They use a pair of NOR gates to perform the dead-time masking, and "uncommitted BJT" outputs furnish active-low or active-high logic outputs, or can be used as switches themselves (up to 200mA). The above example shows the active-low case.

Note that duty cycle and frequency can be controlled directly, frequency as RT pin current and duty as a control voltage. There is (are) internal error amp(s) as well, very useful for constructing a full-wave (half-bridge or push-pull, forward or resonant) SMPS.

Alternately, a delayed rising edge can be used to reduce the duty cycle of each signal independently. We start with the oscillator and T flip-flop to get complementary 50% waves. We delay the rising edge, which can be done using an RCD network between logic gates or other buffering:

Here, IC22C's inputs would be from Q (inputs tied, using the NOR gate as an inverter), and IC22B cleans up the slow rising edge from the network. IC22B can also be used as a global input for disabling the output (which it was, from the schematic this was excerpted from).

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In the interests of experts showing off their circuits, for those entertained by discrete circuits, this one will do:

^{Source: Flip-Flop | Tim Williams}

I used 330 ohm collector resistors, 2.2k base-supply resistors and 680 ohm base-turn-off resistors.

Proof of operation:

(2µs/div, 2V/div)

Isn't that a pretty circuit? Shame it takes so many components, but it'd be right at home on an IC.

Answer 3

This Falstad logic circuit is an inverting pulse distributor. (The link will bring you to an online live version.)

The relationship between the input (CLK) and the outputs is shown in this simulation oscillogram

As mentioned, this is an inverting pulse distributor, so a low on the CLK input results in a high value at one of the outputs. The circuit produces high values at alternating outputs.

This circuit can be of value in distributing a single pulse train into two interleaved pulse trains.

Note that the the input clock need not have a 50% duty ratio. Indeed, in the simulation, the clock has a 20% duty ratio.

Be aware that there are other ways to implement the same functionality. The above method has the drawback that it may not have the smallest package count if implemented in logic ICs.

Another implementation that may have a smaller package count, but which relies upon an edge triggered D flip-flops is this.

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Any circuit with the above functionality can be combined with a divide-by-5 counter, such as the divide-by-5 section of the 74LS90 or one of the sections of a 74HC390 to make a 20% duty ratio clock. (The latter chip has a higher "high" voltage, and its outputs are compatible with a greater variety of other chips. However, it is larger, has more pins, and is usually more expensive.)

When fed with a 1 MHz clock, a 200 kHz 20% duty ratio pulse stream is produced.

This can be fed into the pulse distributor to give 2 pulse trains of 100 kHz 40% duty ratio each. Note that you need to use components from compatible logic families throughout.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 4

Note the tags in the question didn't mention digital so, I aimed for a solution that is closely analogue: -

Make a precision triangle wave generator like this: -

Image from Precision Triangular-Wave Generator.

Then use a pair of comparators (faster the better); one to produce a positive output when the triangle waveform reaches above a positive_threshold. The other comparator is wired to produce a positive output when the triangle waveform falls below a negative_threshold.

Both thresholds can be adjusted independently of course but, for your application, the negative_threshold should be mid-triangle-voltage minus positive threshold i.e. use an inverting op-amp fed from the positive_threshold.

Answer 5

You can use a NE555 or better a faster, compatible timer circuit to create a sawtooth signal at capacitor C1.

The connected two comparators produce square wave outputs by comparing the sawtooth signal with a DC voltage. The simulator does not offer comparators, so I use very fast OpAmps there.

R3 defines the small difference between the two compare levels and defines the gap, where no comparator output is high.

The phase angle between the outputs is fixed, they are created from one source signal.

The sawtooth signal voltage is symmetrical to half of the supply voltage. The NE555 trigger levels are 1/3 VCC and 2/3 VCC. So R2 and R4 must have the same value.

Such circuits work up to 1 MHz with fast comparators.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 6

Use an ARM Cortex based microconroller something like the STM32G030xx microcontroller. This is an example choice. There are many others.

You can get it in 8/20/32/48-pin versions. Needs an external oscillator, some power conditioning and not much else. Timer 1 is an advanced timer that will generate the pwm signals for a full bridge complete with dead time.

This is a fairly complex problem

The micro can handle compex problems.