# Problem generating two asymmetrical pulse waves

I am trying to generate two pulse waveforms with a on to off time ratio of around 40/60. The max amplitude is only 5 V however the switching frequency is quite high at around 100 kHz.

The two waveforms should have a phase offset of around 180 degrees, resulting in the on time of one wave lining up exactly between the off time of the other. It is imperative the phase relationship stays the same.

I have designed a quick diagram below to show what I'm aiming for:

I have tried multiple solutions. I am aware a micro can easily do this but I would want a discrete solution if possible.

I have tried the following:

• A 555 timer. This did generate one waveform however I don't know how to generate another waveform that has the correct phase relationship (e.g. two separate 555 timers won't 'line up').

• A astable multivibrator. This is presented the same issue as above.

I would really appreciate any input. This is a fairly complex problem so I'd be interested other what people think. Thank you.

• Did you mean µs not ns? Commented Aug 4, 2023 at 18:35
• I would use a PLC Commented Aug 4, 2023 at 18:35
• Yes I did - I fixed the image, thank you Tim. Commented Aug 4, 2023 at 18:40
• Hi Voltage Spike, unfortunately this design needs to sit on a PCB so a PLC isn't really suitable. Its more a case of wanting to use discrete components for the design before resorting to a digital solution. Commented Aug 4, 2023 at 18:42
• is the perference for an analog solution personal? What are your requirements regarding drift, jitter, stability, etc.? We used an 555 for a duty cycle circuit in a design due to the electronic component shortage last year and I really regret it by now because it is very sensistive to components variantions and generates unexpected artefacts (sporadic pulses). Commented Aug 4, 2023 at 19:56

This idea uses five of the six the schmitt-trigger input inverters of a 74HC14 package:

simulate this circuit – Schematic created using CircuitLab

The first gate G1 is a relaxation oscillator running at about 100kHz, producing a roughly square wave at SQ, which is buffered by G2. G2 and G3 outputs are inverted with respect to each other, and used to feed the next stages.

The diode, capacitor and resistor networks produce ramps at the inputs of G4 and G5. The charging path impedance during ramp up is different from ramp down, due to the diode, which pushes the duty cycle away from 50%.

G4 and G5 convert the ramp signals back to digital.

The result is something like this:

The initial delay prior to 10μs is just the oscillator starting up, settling into its rhythm.

These simulated gates have less input hysteresis than real 74HC14 gates, so the resistor values will have to be adjusted to produce the exact frequency and delays you require.

R3 and R6 are marked as variable, because they control the asymmetry of the ramps' rise and fall rate, and will need to be adjusted to obtain the duty cycle you require. You can of course combine R3 and R4 into a single resistance, and R6 and R7 too, once you have determined the required resistances.

The gates must have schmitt trigger inputs for this to work, so don't use a 74HC04. Don't leave any unused gate's input unconnected. Always tie unused inputs high or low.

• 74HC04 can be used, with a three-gate oscillator configuration (handily using up that spare 1/6th), though '14 is still preferable. Or CD4069, 40106, etc. for higher voltages. Note that oscillator duty depends on threshold, so will also have to be calibrated (R1 can be made with two R+D to set rise/fall independently); alternately, double Fclk and add a T flip-flop. Commented Aug 6, 2023 at 6:16
• @TimWilliams I insisted on schmitt triggers since they have many benefits in this application, though perhaps it should have been less an insistence, and more a recommendation. For me, though, the single-gate oscillator and single IC are big selling points. It's moot though, if you need SQ at exactly 50% duty, which should use a T flipflop. Commented Aug 6, 2023 at 8:16
• Hi Simon Fitch, this is quite an impressive solution, thanks for looking in to it. I'm having a look at the circuit, and using the diode to change the rate of discharge is a clever way of doing it. I agree with your point about the advantage of using this IC being a single chip but in response to the point made by Tim I already have a square wave oscillator being used elsewhere so I could actually use that (longs that it is buffered)? Many thanks, Simon Commented Aug 6, 2023 at 17:46
• @SimonPCB Sure, you can replace oscillator G1, R1 and C1 with your existing signal (as long as it's square, 50% duty). Matched output impedances of G2 and G3 is good, so I recommend keeping G2. Or, if your signal source has complementary outputs, like a 74HC74 flip-flop with $Q$ and $\overline{Q}$ outputs, they will be well matched, and can directly drive the diode/resistor/capacitor nets, so you could probably dispense with G2 and G3 too. The 74HC14 has good output current though, no harm in keeping G2 & G3. Commented Aug 7, 2023 at 2:09

You need a toggle flip-flop to generate alternating pulses -- this gives you an exact 50% reference -- and then some logic to AND the Q and /Q outputs with the clock. The clock waveform can have a high duty cycle, to implement the dead time. (This is an SMPS application, right? You don't have to hide it.)

Such logic is integrated in push-pull SMPS controllers such as SG3524, TL494 and UC3525. Here is an example:

For which the block diagram is:

The oscillator's output is low while the capacitor charges (through a current mirrored from the RT pin), and high while it discharges (through an internal switch that draws more current). Thus a low duty cycle is created. They use a pair of NOR gates to perform the dead-time masking, and "uncommitted BJT" outputs furnish active-low or active-high logic outputs, or can be used as switches themselves (up to 200mA). The above example shows the active-low case.

Note that duty cycle and frequency can be controlled directly, frequency as RT pin current and duty as a control voltage. There is (are) internal error amp(s) as well, very useful for constructing a full-wave (half-bridge or push-pull, forward or resonant) SMPS.

Alternately, a delayed rising edge can be used to reduce the duty cycle of each signal independently. We start with the oscillator and T flip-flop to get complementary 50% waves. We delay the rising edge, which can be done using an RCD network between logic gates or other buffering:

Here, IC22C's inputs would be from Q (inputs tied, using the NOR gate as an inverter), and IC22B cleans up the slow rising edge from the network. IC22B can also be used as a global input for disabling the output (which it was, from the schematic this was excerpted from).

In the interests of experts showing off their circuits, for those entertained by discrete circuits, this one will do:

Source: Flip-Flop | Tim Williams

I used 330 ohm collector resistors, 2.2k base-supply resistors and 680 ohm base-turn-off resistors.

Proof of operation:

(2µs/div, 2V/div)

Isn't that a pretty circuit? Shame it takes so many components, but it'd be right at home on an IC.

• Hi Tim, thanks for that reply. The application is actually for a H-Bridge drive. I didn't mention it as I wanted to keep the question concise. As you can see the reason for the large 'gaps' is to prevent shoot through on the bridge (where both sides conduct at the same time). In response to your reply I see what you mean about a signal with a 50/50 duty cycle, but I'm a bit confused by what you mean with the clock. I am using an AND gate to combine this with the 50/50 signal but what would the clock waveform look like i.e. how do I create the phase offset? Many thanks Commented Aug 4, 2023 at 19:03
• Tim, thanks for the further detail. I wasn't aware that was the logic some IC's used. Unfortunately as this is for motor control I can't use a push pull chip as that would have been a nice solution. Your explanation has helped me understand how the circuit works. It seems a lot of the answers here use gates on the waveform generation. I will have to consider the stability of the circuit if I use a RCD circuit to delay the rise time as I imagine temperature and component tolerance overt time could have an effect? Oooh is that your circuit? I had a look at the page and its nice work if so :). Commented Aug 6, 2023 at 18:22
• FYI, it's not clear what relevance "motor control", "push pull" or "stability" is here, as you didn't specify tolerances at all, nor how timings might be intended to vary, just a particular waveform (and you indeed intentionally kept the question abstract from even any power switching application). Conversely, choice of specific gates or other implementation doesn't seem very important to the answer. It sounds like you may have further questions in that direction (implementation, component choice, power design and control) though; feel free to ask those separately. Cheers! Commented Aug 6, 2023 at 18:45

This Falstad logic circuit is an inverting pulse distributor. (The link will bring you to an online live version.)

The relationship between the input (CLK) and the outputs is shown in this simulation oscillogram

As mentioned, this is an inverting pulse distributor, so a low on the CLK input results in a high value at one of the outputs. The circuit produces high values at alternating outputs.

This circuit can be of value in distributing a single pulse train into two interleaved pulse trains.

Note that the the input clock need not have a 50% duty ratio. Indeed, in the simulation, the clock has a 20% duty ratio.

Be aware that there are other ways to implement the same functionality. The above method has the drawback that it may not have the smallest package count if implemented in logic ICs.

Another implementation that may have a smaller package count, but which relies upon an edge triggered D flip-flops is this.

Any circuit with the above functionality can be combined with a divide-by-5 counter, such as the divide-by-5 section of the 74LS90 or one of the sections of a 74HC390 to make a 20% duty ratio clock. (The latter chip has a higher "high" voltage, and its outputs are compatible with a greater variety of other chips. However, it is larger, has more pins, and is usually more expensive.)

When fed with a 1 MHz clock, a 200 kHz 20% duty ratio pulse stream is produced.

This can be fed into the pulse distributor to give 2 pulse trains of 100 kHz 40% duty ratio each. Note that you need to use components from compatible logic families throughout.

simulate this circuit – Schematic created using CircuitLab

• Hi Math Keeps Me Busy, this is a very interesting solution. Would the clock rate of 1 MHz be too high for the decoding circuits or not? I haven't used any at this speed before. I'm just trying to visualise the solution to see if this would fit in my design, in terms of the decoding at the end would the decoder circuit be an off the shelf component? I imagine it would be a combination of logic gates. Thanks for our reply, this is quite interesting. Commented Aug 5, 2023 at 14:22
• No, 1 MHz is fine for virtually all logic families. If the decade counter is configured as a divide by five, first, followed by a divide by 2, I think the decoding at the end could fit in one or two chips. I have to go out for a bit, but let me work on that since you seem to be interested. Commented Aug 5, 2023 at 14:25
• @SimonPCB I have updated my answer. Commented Aug 6, 2023 at 13:52
• There is a simpler form: Q and /Q from one 'T' can be ANDed with CLK straightaway. Though you might not have anything else to use the other half 74HC74 (for example) on, making it a wash at the PCB level (package count). Commented Aug 6, 2023 at 14:11
• Hi Math Keeps Me Busy, thank you very much for taking the time to simulate the circuit. The second solution with the Flip Flops was something I was initially toying with but I was also concerned about the hold times for the flip flops, if I wanted to alter the frequency for whatever reason I could be limited. Your last point has made it clearer to me what you initially meant. I didn't fully understand how you generated the 20% wave but it makes total sense now using the 1MHz clock and dividing it down by 5. I imagine the only factor affecting instability in the last circuit is the crystal? Commented Aug 6, 2023 at 18:10

Note the tags in the question didn't mention digital so, I aimed for a solution that is closely analogue: -

Make a precision triangle wave generator like this: -

Image from Precision Triangular-Wave Generator.

Then use a pair of comparators (faster the better); one to produce a positive output when the triangle waveform reaches above a positive_threshold. The other comparator is wired to produce a positive output when the triangle waveform falls below a negative_threshold.

Both thresholds can be adjusted independently of course but, for your application, the negative_threshold should be mid-triangle-voltage minus positive threshold i.e. use an inverting op-amp fed from the positive_threshold.

• Hi Andy aka. This makes a lot of sense now I think about it. I was initially toying with the idea of using a sine wave but a triangle wave makes so much more sense as obviously it is easier to choose which points I trigger from. Making a triangle wave isn't too difficult either as you've shown. Many thanks for your help Commented Aug 5, 2023 at 14:26
• @SimonPCB if we are done here, please take note of this: What should I do when someone answers my question. If you are still confused about something then leave a comment to request further clarification. Commented Aug 5, 2023 at 15:05
• Hi Andyaka, apologies for the delay. As you can see there are a lot of answers to look through and I am looking into each one in depth as they are quite different so I have not formally selected 'the best' answer yet. I am aware of the procedure on marking questions when answered, especially as I have had many helpful replies. Commented Aug 6, 2023 at 17:58
• @SimonPCB the bit I was attracting you to was this: Decide if the answer is helpful, and then... Vote on it (if you have earned the appropriate voting privilege). <-- you have the reputation to vote on all answers that are useful. If you didn't find my answer helpful then I guess time will reveal that to me. Commented Aug 6, 2023 at 19:04
• @SimonPCB you also linked the "analog" tag into your question yet, you have chosen a more digital solution as your preferred answer. I also point you towards the conversation you have with christianB and note that your preferred answer is going to be very poor in this respect because Schmitt trigger threshold levels are not very well defined for logic inverters and, one of you outputs suffers an extra digital delay. I'd be concerned about this. My solution is about as analogue as you can get. Commented Aug 6, 2023 at 19:37

You can use a NE555 or better a faster, compatible timer circuit to create a sawtooth signal at capacitor C1.

The connected two comparators produce square wave outputs by comparing the sawtooth signal with a DC voltage. The simulator does not offer comparators, so I use very fast OpAmps there.

R3 defines the small difference between the two compare levels and defines the gap, where no comparator output is high.

The phase angle between the outputs is fixed, they are created from one source signal.

The sawtooth signal voltage is symmetrical to half of the supply voltage. The NE555 trigger levels are 1/3 VCC and 2/3 VCC. So R2 and R4 must have the same value.

Such circuits work up to 1 MHz with fast comparators.

simulate this circuit – Schematic created using CircuitLab

Use an ARM Cortex based microconroller something like the STM32G030xx microcontroller. This is an example choice. There are many others.

You can get it in 8/20/32/48-pin versions. Needs an external oscillator, some power conditioning and not much else. Timer 1 is an advanced timer that will generate the pwm signals for a full bridge complete with dead time.

This is a fairly complex problem

The micro can handle compex problems.

• Hi RussellH, this is true. I have been fortunate enough to get a range of interesting solutions here which I'm going to evaluate first. The reason I didn't want to use a Micro is although I have experience with them I wanted to avoid sticking with a particular IC as the design grows or changes. I do see the advantage though and depending on the stability of the solutions here (as others have pointed out), using a Micro may be more stable and consistent. Commented Aug 5, 2023 at 14:29