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I've build a daisy chain of 3 x 74HC595 shift registers with LEDs on their outputs. They are fed by an Arduino that is pushing a single bit through all the registers and will finally clear the register via the MR pin.

Pushing the bit seems to work fine, but when it comes to the last shift register, something strange happens: When the bit reaches Q6, Q7S on that register also lights up. Then Q6 (and Q7S) go dark and only Q7 lights up.

I can't figure out why Q7S lights up on the last register. I've also changed the register with a new one, but the problem persists.

Maybe I've got a misunderstanding about the workings of the 74HC595, but I'd expect Q7S only to light up AFTER Q7.

Any things I should look into?

edit: This is my schematics. Each ROW/COL pin on the shift registers is connected to an LED which is then connected to GND.

enter image description here

This is my test code:

void setup() {

  #define DS 4
  #define STCP 6
  #define SHCP 7
  #define MR 8

  pinMode(DS, OUTPUT);
  pinMode(STCP, OUTPUT);
  pinMode(SHCP, OUTPUT);
  pinMode(MR, OUTPUT);

  #define NUM 24

}

void loop() {

  // clear everything from registers
  digitalWrite(MR, LOW);
  delay(100);
  digitalWrite(MR, HIGH);

  // shift 1 bit through all registers
  for(int i = 0; i <= NUM; i++) {
    // activate storage mode
    digitalWrite(SHCP, LOW);

    // set only the first bit to high
    digitalWrite(STCP, LOW);
    if(i == 0) {
      digitalWrite(DS, HIGH);
    } else {
      digitalWrite(DS, LOW);
    }
    digitalWrite(STCP, HIGH);

    // disable storage mode / write data to output register
    digitalWrite(SHCP, HIGH);
    delay(200);
  }

  delay(2000);

  // turn them all off
  for(int i = 0; i < NUM; i++) {
    digitalWrite(SHCP, LOW);

    digitalWrite(STCP, LOW);
    digitalWrite(DS, LOW);
    digitalWrite(STCP, HIGH);

    digitalWrite(SHCP, HIGH);
  } 

}
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    \$\begingroup\$ So how do you drive it, have you by any chance tied the SRCLK and RCLK pins (11 and 12) together? \$\endgroup\$
    – Justme
    Commented Aug 5, 2023 at 20:56
  • \$\begingroup\$ Well, I've connected SRCLK and RCLK (and also MR) across the registers, but there are no cross connections between them. What do you mean by driving them besides that? \$\endgroup\$
    – flomei
    Commented Aug 5, 2023 at 21:34
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    \$\begingroup\$ Why are you even looking at "Q7S". That output is just meant for daisy-chaining, and it's working exactly as it should. \$\endgroup\$
    – Dave Tweed
    Commented Aug 5, 2023 at 21:36
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    \$\begingroup\$ @flomei Please post schematics and code. I simply wanted to know how you are conncting or controlling SRCLK and RLCK, are they connected together as single clock from MCU or how doea MCU code controls the pins. Because it may explain the behaviour. \$\endgroup\$
    – Justme
    Commented Aug 5, 2023 at 22:20
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    \$\begingroup\$ Check Q7S of the previous stages, they behave the same. This avoids clock ripple errors. \$\endgroup\$
    – Jens
    Commented Aug 6, 2023 at 0:02

1 Answer 1

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Your code sets both SRCLK and RCLK high effectively at the same time, with only a short delay between them.

The data sheet says that in such case the shift register is always one clock pulse ahead of the storage register.

If that does not explain it, then you also give 25 clock pulses, not 24, in the for loop that turns bits on. So it will definitely leave the QH' output of shift register high. Note the correct 24 pulses is given in the loop that turns bits off afterwards.

Also LEDs cannot be directly connected to chip output like that, it pulls too much current without a resistor.

There is also no bypass caps drawn for the shift registers. The sudden current spike drawn by the chip on each clock pulse may cause momentary drop in the chip supply and it may work erratically.

All these may contribute to weird behaviour, but at least the code specifically leaves the LED on.

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  • \$\begingroup\$ I've added the protective circuitry and added a slight delay to give SRCLK and RCLK to work their magic. The effect stays the same. Although, as @Jens has pointed out, this also occurs on the Q7S of the second register and seems to be a feature rather than a bug? \$\endgroup\$
    – flomei
    Commented Aug 6, 2023 at 23:49
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    \$\begingroup\$ @flomei Ah so it might be you expect the chip to work differently? It can't, the QH' output is from the shift register, it has to go through the chips with the bit shift clock. The QA..QH outputs are from the latch that capture the shift register output to the actual output pins. So the QH' has to be high if you want RCLK to transfer a high to output. \$\endgroup\$
    – Justme
    Commented Aug 7, 2023 at 5:42

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