0
\$\begingroup\$

I am working on a non-FIFO queue design using flip flops to store data elements. During testing, I encountered an issue where reading the value from a flip flop after storing a new value in another flip flop does not yield the expected result. Specifically, when I store value A to flip flop A at the first cycle and then store value B to flip flop B at the next cycle, attempting to read the value from flip flop A at the third cycle returns a zero instead of the value A that I initially stored.

I am using a clocked sequential design with separate write and read enable signals to perform enqueue and dequeue operations. The control signals for enabling the flip flops are synchronized with the clock signal.

I have reviewed the clocking, reset signals, and timing constraints, but I cannot identify the cause of this unexpected behavior. I have also verified the connections and data paths, but everything seems correct.

Could anyone suggest potential reasons for this issue or provide guidance on how to troubleshoot and resolve the problem? Any insights, advice, or best practices to ensure proper data storage and retrieval in a non-FIFO queue design using flip flops would be greatly appreciated.

enter image description here

enter image description here

\$\endgroup\$

1 Answer 1

0
\$\begingroup\$

Your schematic shows that you clock all flip flops in parallel, that's good.

But also in parallel you switch all data inputs of the flip flops unconditionally with Write_en between their own output and the output of the input demultiplexer Inst. This demultiplexer sets all unselected flip flop inputs to zero.

Finally, you have this additional AND Inst22 in the feedback of S1 (Inst3), which clears the input data on Write_En = 1.

In consequence, you write zero to any unselected flip flop. And you made it double-safe for S1 with the AND. See this annotated schematic of yours:

enter image description here

One possible solution is to switch the individual input multiplexers in dependence of Write_addr.

And remove this AND...

enter image description here

\$\endgroup\$
5
  • \$\begingroup\$ Hi, can you show the schematic as it is a bit confusing when reading the text-based design? Sorry for any inconvenience caused. \$\endgroup\$
    – CJ. T
    Commented Aug 7, 2023 at 8:08
  • \$\begingroup\$ @busybee, what do you mean by 'switching the individual input multiplexers in dependence of Write_addr'? \$\endgroup\$
    – CJ. T
    Commented Aug 7, 2023 at 8:43
  • \$\begingroup\$ As a coming digital logic developer you need to learn to understand text. Drawing schematics takes commonly longer than using a textual representation, think about VHDL. I just donated you several minutes of my precious spare time. -- See my edit for the presented idea. \$\endgroup\$ Commented Aug 7, 2023 at 9:41
  • \$\begingroup\$ Thanks, @busybee. What is your advice if I change the D flip-flop to D latch, i.e., transferring from edge-triggering to level-triggering? \$\endgroup\$
    – CJ. T
    Commented Aug 7, 2023 at 13:48
  • \$\begingroup\$ You might want to take the tour to refresh how this site works, for example how to say "thanks". ;-) -- Concerning the trigger of flip flops, this is a separate issue. And if it is important for you, please post a new question. Anyway, you should meditate on it yourself to learn more. It depends heavily on the requirements for your system. Just think about the implications of the "transparency" of level-triggered flip flops. \$\endgroup\$ Commented Aug 7, 2023 at 14:12

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.