I'm currently studying for finals (I have the solutions here already, so this isn't helping me bypass doing homework or anything like that.)
My professor has done an unsatisfactory job explaining this particular circuit's step-by-step functioning and so I'm really confused:
- how the columns are being generated and
- how the errors are detected.
If anyone could help explain how this is working, I would appreciate it very much.
Problem: For the single error correcting code circuit, fill in the response to reception as far as necessary, and determine if any error is detected and, if so, what symbol is corrected.
Solution: the second from last position is corrected, yielding 0110100, time from left to right.
UPDATE: I think I finally have a hard-fought understanding of this circuit, except for one issue. If you could take a look at this proposed explanation and see if it's correct, I would again be very appreciative.
This is an error-detection circuit. It will tell you where the error in the given codeword is by outputting a 1 on the upper right. For the first seven digits of the codeword that are input, they are stored in the register as well as cycled through the feedback shift register in order to arrive at the 3 bits on the seventh timing. If these three check bits are nonzero, then there is an error. The right-hand side of the AND gate is enabled on the seventh timing, meaning the output of that AND gate will be a 1 when the input to the previous AND gate is a 001.
So, we wait for the shift feedback register to keep cycling through itself (the upper line of the XOR that goes into the shift feedback register is constantly 0 during this post-seventh timing cycling process, so it's always the contents of the final register XOR'd with 0). Once 001 manifests itself in the three registers, the AND gate outputs a 1 and is XOR'd with the given 7-unit delay register contents, yielding the location of the error.
The issue that I have with this is that it says the the correct solution is that the error bit was in the second-to-last bit. Is the error not in the third-to-last bit because we must wait until the clock refreshes in the registers for the 001 to be pushed into the AND gate in the thirteenth timing?