0
\$\begingroup\$

So I have a 48 V system with an STM32 controlling a gate driver which has a 12 V supply switching MOSFETs on the 48 V rail. Occasionally, for whatever reason that doesn't form part of this question, the system gets unhappy and the gate driver releases 48 V into... Other things.

I think it mainly gets onto the 12 V rail. This is easily dealt with by having a diode between the 12 V PSU and the gate driver 12V. I think this has been the failure mode since the 3.3 V and 5 V regulators toasted.

The other place it could be getting to is the STM32 line s connected to timer 1 pins. PA8 9 10 and PB13 14 15.

The question is how to protect this such that the MCU remains not dead. It's logging and I would like to retrieve those logs. If it remains repairable by changing the gate drivers that's even better.

I'm thinking it's basically impossible to kill things with 48 V through a sufficiently large resistor. 1 MΩ would obviously make it completely immune regardless of the st injected specs, you can't even feel 240 V through 1 MΩ. But 1 MΩ would probably also make the lines sensitive to noise and the drivers have a 100 kΩ pull down so that would be hopeless.

10 kΩ probably would drive the gate driver, but fast enough? It needs ~50 ns accuracy. There's about 500 ns dead time and 20 kHz PWM so that sets the expectation. But would this protect the STM?

Is there any other simple cheap low board space method for dealing with this?

Edit: I'm using a standard bridge with large toll MOSFETs and ir2181 style drivers (copies due to availability). The proposition is to put the high impedance between the ir2181 and the stm.

It's running a motor, 3 phase, and I'm pushing it deep into flux weakening so when that collapses the voltage generated is several times the bus voltage, the mos blow, high voltage EVs up on the gate lines, general not nice ness. Edit 2: schematic spring the general design. This question applies to all boards if this type.

\$\endgroup\$
7
  • 2
    \$\begingroup\$ System diagram needed. || A gate driver driver that is 48V immune would fix feedback via the drive line. This could be n NPN and PNP transistor pir, bases joined and driven via an R from STM. Zner on STM sid of drive resistor. emitters joined and driving gate driver. collectors to relevant 12V supply and ground. || Any other path is a matter of improve design being needed. The gate-driver should be able to have it's own supply connected to the rest of the system only by ground. || You do not say WHY the other pin should be affected, but there is no obvious reason that they should be. \$\endgroup\$
    – Russell McMahon
    Aug 10, 2023 at 3:36
  • \$\begingroup\$ My answer added to. \$\endgroup\$
    – Russell McMahon
    Aug 11, 2023 at 12:37
  • \$\begingroup\$ A system diagram is needed. \$\endgroup\$
    – Russell McMahon
    Aug 13, 2023 at 6:31
  • \$\begingroup\$ As long as the MOSFETS are rated for the maximum voltage spikes then this MAY help.: Add a zener to each MOSFET gate-source rated at somewhat above max intended drive voltage. Mount as physically and electrically close as possible to the FET g-s connections. The zeners stop drin spikes from Millar coupling the to the gate and overdriving the gs potential above Vgsabsmax. Doing this breaks down the gate oxide and "away we go". This MY save you from HV spikes below VDSmax. || Less likely to help in this context but a bonus - reverse polarity small Schottky connected g-s. \$\endgroup\$
    – Russell McMahon
    Aug 13, 2023 at 6:37
  • \$\begingroup\$ Spikes above Vds max need a hard clamp to prevent them. A suitably severe clamp to the power supply may help. An active clamp my help - MOSFET turned on by suitably high motor voltage hard clamps to supply. That FET is always on or off - perhaps with a small series load to set Imax appropriately. "SuperSnubber" :-) \$\endgroup\$
    – Russell McMahon
    Aug 13, 2023 at 6:57

1 Answer 1

0
\$\begingroup\$

System diagram needed.

A gate-driver-driver that is 48V immune would fix feedback via the drive line.
This could be

  • An NPN and PNP transistor pair,
  • Bases joined and driven via an R from STM.
  • Zener on STM side of drive resistor.
  • Emitters joined and driving gate driver.
  • Collectors to relevant 12V supply and ground.

Any other path is a matter of improve design being needed.
The gate-driver should be able to have it's own supply connected to the rest of the system only by ground.

You do not say WHY the other pin should be affected, but there is no obvious reason that they should be.


Example only:

Add drive resistor from STM, clamped with a Zener. Wattages to suit.

From my SEEE answer here

enter image description here


ADDED:

I can't really see the answer in this. There's no logic level MCU, no gate driver, and I see no reason that this arrangement would fair any better during failure of the switch MOSFET and npn pnp pair than my one does during failure of the gate driver.

The answer is in the text.
It may indeed not be useful, as you say.
But it gives you a protectable customisable buffer between the badly behaving driver and the STM32.
The diagram is only an example of the pnp/npn arrangement that is mentioned.

You said

Occasionally, for whatever reason that doesn't form part of this question, the system gets unhappy and the gate driver releases 48 V into... Other things.

ie you said that the gate driver was doing bad things. That is what I am addressing.

Your gate driver input needs to be isolated from what is driving it's input. It MAY be that you can drive it with 10K as you say. I do not know it's input capacitance or other characteristics.

Adding this predriver gives you a designable very low component cost buffer. You can split the rise times between the driver and the driver-driver.

If you drive this circuit with a 1K and say 4V7 input zener you'll need about a 1 watt resistor ((24-5)^2/1k dissipation) and a 500 mW zener would be very ample.

ALL the other possible paths that you mention are not necessary - based on the information provided. There should be no other 24V paths into the STM system unless there are signals involved that you haven't mentioned.

As ever - System diagram needed.

\$\endgroup\$
2
  • \$\begingroup\$ I can't really see the answer in this. There's no logic level MCU, no gate driver, and I see no reason that this arrangement would fair any better during failure of the switch MOSFET and npn pnp pair than my one does during failure of the gate driver. \$\endgroup\$ Aug 11, 2023 at 4:26
  • \$\begingroup\$ Perhaps if i ignore the rest of your answer and just take "Bases joined and driven via an R from STM. Zener on STM side of drive resistor." That might work, using the Zener to further suppress any damaging voltages with the resistor limiting current. \$\endgroup\$ Aug 11, 2023 at 4:28

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.