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I'm laying out a step down converter based on the ST L5973AD being used in constant-current layout to drive LEDs, per Application note 2823.

My previous question was what is the datasheet telling us to do, whose answers were basically keep the low-current far from the high-current. My question here is please review my basic layout. The other component values are not yet fixed, but their sizes are typical. In any case, it's the general arrangement about grounds that I'm really asking about.

  • I have positioned the current sensing resistor (typ 0R68) on the high-current side with a smaller track to the feedback circuit R1-R2-R3. My reasoning is that it has full LED current through it, and negligible current coming from the bottom of R2. Q1. Is this a good position?
  • Some of the tracks require either vias or track under a component or go say 20 mm further. (For general-purpose signals, say 500 kHz digital, 3V3, negligible current.) Q2: is there a rule-of-thumb for which to prefer? (Examples on this circuit: Vref through R2)
  • For the ground plane, here for thermal purposes (as I understand it), Q3: should I remove the thermal relief on the bottom pad of U1?

Circuit diagram, following Application note 2823 fig 5..
enter image description here

enter image description here

enter image description here
This is what ST says to do: ST Application Note 1723. You can't see it here, but the ST's real PCB has the ground connected vertically under the chip on the top layer, but not the bottom layer.


Edited to add:

ST's evaluation board (slightly different circuit, has no current sense R3) from ST, note vias. There are also ten very small vias under the chip1.

enter image description here

Footprint comparison: on the left is the recommended "SOIC127P600X170-9N" footprint from ST's CAD models. On the right the one I used which is almost the same except a) pad on bottom, b) vias. Note that ST's actual board had ten vias under the chip to the bottom ground plane. enter image description here

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    \$\begingroup\$ There's a pad on the bottom side? But the component is on top? ...Why? \$\endgroup\$ Aug 13, 2023 at 16:17
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    \$\begingroup\$ There is thermal relief on U1 thermal pad on the bottom. Why? \$\endgroup\$
    – RussellH
    Aug 13, 2023 at 16:41
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    \$\begingroup\$ There is a spilt in the bottom side ground plane. Why? \$\endgroup\$
    – RussellH
    Aug 13, 2023 at 16:46
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    \$\begingroup\$ Do you really need the vias on U1 thermal pad? The way the ground plane is cut does not make sense to me. \$\endgroup\$
    – Ralph
    Aug 13, 2023 at 16:47
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    \$\begingroup\$ Here is a good discussion on pcb ground.. Rick Hartley has alot of good stuff. \$\endgroup\$
    – RussellH
    Aug 13, 2023 at 21:12

3 Answers 3

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As in the other answer, R3's position looks good. You might just want to keep the trace going to R2 further away from the input power trace.

For R1 and R2, you might turn those both horizontal, that could give you more flexibility to run the traces more efficiently.

The potential problem with your thermal connections is that you are not providing a compatible pad for the chip's underside thermal pad. (See an example foot print here ). In AN1723 this may not be so clear, but look closely at the assemble photo (figure 1 of the note), at the top and bottom edges of the chip you can see open solder mask going under the chip, the top side copper is soldered directly to the chip's heat pad. You could replicate this by extending the thermal pad (of the example foot print) slightly beyond the edges of the chip, that would allow you to verify the solder flow.

Per your later comment on reducing thermal resistance, to do that you want to increase the connection area not restrict it with a thermal relieve.

Your connection to the top ground plane section is less than ideal. For an improvement first stack R4, C3, and C4 and move them a bit to the right, then give a wide connection to the top ground plane section that continues under the chip. In AN1723 figure 7 you can see that the two ground plane sections (top copper) come together near the chip's ground pin.

It may help to rotate C1 CW and slide it slightly left, then move D1 up slightly. This can help reduce the size of the high current loop (L5973AD pin 1 to 8), this can minimize EMI and resonance problems, (as mentioned in AN1723 figure 16).

A bit on split ground planes: In some cases it helps to partially split a large ground plane then have it reconnect at a single common point. This can reduce the possibility of high ground current paths (or loops) from passing close to sensitive circuits and causing undesired noise. In this case there is a high ground current loop passing between D1 and C1.

(I also corrected your two links to AN2823)

.

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  • \$\begingroup\$ In the end, I got rid of sync as I didn't intend to use it for more than an experiment. I put the ground plane almost uninterrupted across the bottom, and filled everywhere on top, carefully separating tracks so there was ground fill between most signals. I used a modified footprint for the regulator with a big exposed pad on top, extending as you say a tiny amount. Vias joining top and bottom ground every 2 mm or so. \$\endgroup\$
    – jonathanjo
    Sep 20, 2023 at 11:20
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  • R3 is in good position, as you reasoned, no reason to have the higher current travel any further than necessary
  • If you bring the components further apart, you'll be wasting board space and possibly creating some antennas, even if the signal on your design is slow, which may cause problems in EMC radiated immunity testing. For example it's good to keep R2 near the IC and routing VREF underneath is ok.
  • You can remove the thermal relief on bottom layer. Without knowing the specifics, the vias on the thermal pad can be removed too.

Also:

  • The VREF output from L5973AD cannot output much current. Consider adding a 3.3 V power supply on the board
  • Remove the copper pour split in the bottom layer. Especially if you plan to route the VREF and GND to the rest of the ciruit from the upper part of the PCB.
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  • \$\begingroup\$ R3: glad I got the principle correct. "It is good as is": I'm sorry, what is good as is? Thermal on bottom: understood. Vias on thermal pad are just copied from eval board / library footprint. What do you recommend? VREF current limit is noted, known good for my application. Copper pour split on bottom: copied from eval board, I'd have had a single whole-board bottom pour. \$\endgroup\$
    – jonathanjo
    Aug 13, 2023 at 21:06
  • \$\begingroup\$ Clarified that I meant the VREF track in your design is ok. Vias on the thermal pad are just a complication for the manufacturing, so I wouldn't put them in, unless it's needed. \$\endgroup\$
    – Ralph
    Aug 14, 2023 at 4:27
  • \$\begingroup\$ Maybe the picture is not displaying the complete GND plane. From the picture it looks like there would be a ground loop forming. The point is that you want to avoid the return currents from interfering with other signals, for that just a partial split in the GND plane is enough. \$\endgroup\$
    – Ralph
    Aug 14, 2023 at 4:37
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Some comments that haven't been aired yet:

  • Not nearly so many vias are necessary. This density would be sufficient for ~GHz RF designs. Just a few near critical components/pads, and around corners, traces, etc. will do. Mind the inside loops of critical current paths.

    To be clear: there is little downside to more vias, on a 2-layer board, until you have so many that either the board fab complains and adds a surcharge, or the board falls apart from being Swiss cheese. This is more a comment about understanding than practice.

    Also to be clear, via density can matter (in EM terms) on multilayer, as each via creates negative space in planes on nets different from the via's. (On a 2-layer board, there's nothing else to stitch to, so this can't happen.)

  • Your "illustrative" diagram somewhat implies that the LED string is off on another board, or through a connector, or at least another region of the same board. In the example layout, it's a short loop hanging off the edge.

    As shown, it's likely not long enough to matter, but the important part is, size matters relative to the switching frequency/harmonics of the converter. If it were LEDs distributed around the periphery of the board, say, then you'd have a loop antenna and additional filtering going into (and out of) the LED string may be warranted. If going to a connector, I would almost certainly add an LC (on each lead!) to whatever EMI ground is nearest the connector.

  • It sounds like you intend to embed this in a larger board or project. Therefore we cannot ignore the ripple or common mode voltages between pairs of connections:

External noise paths annotated

  • There are two grounds; which one shall be used as reference?

  • VREF comes off right beside +V, which seems fine to use that side for connections; but SYNC is all the way on the other side. Indeed it's on the far side of a partial ground split, meaning the GND-GND impedance is relatively high to the region that trace will enclose (if brought back around the right and top edges, to join up with the rest of the traces).

  • SYNC can drop under the chip, maybe around the top (near/under R4-C4-C3, say), and then GND can be poured and stitched around much of the active area. With solid GND surrounding the chip and related components, ground-loop currents flow in local loops, and the currents drop off reciprocal with distance*. Whereas with a slot, or higher impedance anyway, local currents can spread out further, and voltage drops across the area are larger (which makes your choice of ground wire, and the relative position of signal traces, that much more important).

  • if SYNC is coming from say an MCU timer, beware that it's quite high bandwidth itself (logic level, rise time of some ns), unless limited suitably (slew rate settings, filtering, etc.). That can carry EMI into the area.

*I don't know offhand, actually, if that's inverse square, or inverse cube (it's a loop / dipole), or exponential (because skin effect), specifically for PCB geometries. Probably a combination thereof, depending on exact geometry, and frequency.


About appnotes (and eval boards): I would be skeptical whether they tested it for anything in particular at all. As Rick Hartley has said, appnotes can be generally assumed "wrong until proven right". In other words: test it yourself, for the particular thing you need to test (like EMC).

Never assume they tested a board for anything more than functional behavior (and even that can be a dubious assumption!). Eval boards, in general, need not be tested for EMC, because they are for lab use only -- not product or integration use, to be operated by a technician in a controlled environment. Depending on use, and market, boards may still be marked for various reasons (safety or EMC), but that still doesn't necessarily mean that it'll meet your levels, or after whatever modifications you intend to do to it, whether in terms of hardware or software; or that you'll even be using it in the same configuration (cable connections, lengths and orientations) as it was tested in.

For my part, I treat appnotes as a starting point, reference information that may contribute to the design process -- almost never a finished solution. Always read critically, I mean generally in life, to be sure, but especially when sources are of known dubious nature, like appnotes.

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  • \$\begingroup\$ Goodness thank you for such an explanatory answer! I'll read it more slowly in the morning. Note re "two grounds": the one in the middle is to the nominal CPU, some low-power 3V3 device powered off the Vref of this circuit. (Shown in circuit diagram; wasn't intending it to be more than a placeholder as what I'm really asking about is ground. In real life the LEDs are very close, about 10 or 15 mm.) \$\endgroup\$
    – jonathanjo
    Aug 14, 2023 at 5:03

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