Does the master-slave JK flip-flop really solve the race condition?

Question

The master-slave JK flip-flop is said to solve the problem of racing, as per many online resources that I've referred to.

However, let's say that the initial state of the flip-flop is CLK = 0, J = 0, K = 0 and Q = 0.

Now, K is turned to 1 while CLK is still 0, i.e. in the next clock cycle, the flip-flop will be reset again, even though it is already in the reset state.

As soon as CLK is turned to 1, the master latch will store the value of 0, even though it is already storing 0. But, if the inputs change and J is turned to 1 while CLK is still 1, then the master latch will now store the value of 1.

This behaviour will occur no matter how far apart in time the changes in the inputs are, as long as CLK is equal to 1 for the entire duration.

So, how exactly does the master-slave JK flip-flop solve racing? I understand that the slave latch will not keep fluctuating depending upon the changes in the input, but the value that goes into the slave once CLK turns 0 is still indeterminate.

On the other hand, this problem is solved in an edge-triggered D flip-flop, where if the initial input to the flip-flop stays that way for a long enough time (called the hold time), then after the hold time elapses, the D input may change to any value while the clock is still high and the changes will not be reflected.

So, in this sense, does an edge-triggered D flip-flop do a better job of preventing racing than a master-slave JK flip-flop?

Answer 1

Theoretically, a circuit has a critical race condition if there exists some arrangement of delays that could be added to the circuit which would cause signals to propagate in a way other than their intended order, and consequently to misbehave.

Practically, the delays in a circuit can sometimes be controlled to a sufficient degree that even though the circuit theoretically has a critical race condition, nevertheless, it never misbehaves (provided its inputs meet certain timing constraints.

The master-slave JK flip-flop theoretically has critical race conditions. However, such master slave flip-flops are almost always manufactured in monolithic ICs. When manufactured in a monolithic IC, the manufacturer can control the various delays within certain bounds. So even though it is theoretically has critical races, in practice we can trust the manufacturer to ensure that the flip-flop will behave as expected, providing the timing constraints on the inputs are observed.

So, although we trust this circuit as provided by a manufacturer, if we implement the circuit ourselves, we become responsible for ensuring critical races do not become manifest. We become responsible for ensuring that possible timing delays in the actual circuit are such that the circuit behaves properly if the inputs meet certain timing constraints.

Answer 2

I'm not sure how you're defining "racing". As mentioned in the other answer, if you buy a circuit pre-made, then certain race conditions are guaranteed to not crop up.

However, any sort of clocked flip-flop system is sensitive to an event where its input voltage changes too close to the clock transition, or where the clock transition is too slow, or where the input voltage has not reached a defined '1' voltage or a defined '0' voltage. All of these situations can cause a condition called "metastability", where the flip-flop is in an indeterminate state.

Search on "metastable" or "digital logic metastable" and you should find plenty of information on this -- like this one, and this one from engineering.stackexchange.com.

Answer 3

Look again at your diagram. First of all, if the Q output is low, the K input has no effect at all, since it is disabled by the feedback. The next state depends only on the J input: if it goes high with sufficient setup time before the falling edge of the clock, the output will go high; otherwise, it will stay the same. Nothing is indeterminate.

The state of the master latch is transferred to the slave latch on the high-to-low transition of the clock. But note that because of the delay of the inverter, the inputs to the master latch are disabled before the inputs to the slave latch are enabled.

On the low-to-high transition of the clock, the master inputs are enabled before the slave inputs are disabled, but this delay is still shorter than the time it would take for any change on the J/K inputs to propagate through two levels of gates in the master latch to the slave inputs.