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I want to get an NE555 chip with a 50% duty cycle to 108-110kHz in output.

I have already experimented with various online calculators and values. However, I never get the values that allow me to do that.

enter image description here

Can anyone help me with the values I need for R1, R2 and C1 to achieve the goal?

P.S. On the calculation page C2 is fixed to 10nF

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  • \$\begingroup\$ Please provide a schematic of what you have tested. R1, R2, and C1 mean nothing without this. \$\endgroup\$
    – earl
    Aug 14 at 15:03
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    \$\begingroup\$ Does this answer your question? Astable 555 timing circuit (0.5 Hz and 50% duty cycle) \$\endgroup\$
    – TimWescott
    Aug 14 at 15:33
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    \$\begingroup\$ The best way to get exactly 50 % is to generate 220 kHz and divide it by 2 using a flip-flop toggled by each clock pulse. A CD4013 or a 74HC74 will do. \$\endgroup\$
    – Uwe
    Aug 14 at 15:48
  • \$\begingroup\$ @Uwe or the very best would be to use a MCU, that pulses out a 110kHz square wave with the 50% duty cycle right? \$\endgroup\$
    – dessi
    Aug 20 at 11:28

4 Answers 4

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The ancient bipolar NE555 can barely make it to 100kHz, so the calculators will not give accurate values, if it works at all.

I suggest you toss it and use a different part such as TLC555 mentioned by @Uwe. The suggested coupling from output will give close to 50% duty cycle if you don't load the output too much and if V+ remains very stable during the cycle (which might not be true if you're driving something that pulls down the power supply). The same circuit with the bipolar NE555 will not give a very accurate 50% duty cycle, particularly at low supply voltage, because the output is very asymmetrical.

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    \$\begingroup\$ Very important information about the restrictions to 50 % with TLC55 or NE555. \$\endgroup\$
    – Uwe
    Aug 14 at 16:36
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This datasheet shows on page 16 figure 17 a special circuit for 50 % duty cycle.

enter image description here

Note that this circuit is for the LMC555 and might not work with the NE555.

A very precise 50 % duty cycle will be achieved by frequency division by 2 using a flip flop like CD4013 or a 74HC74. The 50 % ratio do not depend on the frequency of the clock.

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NE555 is the part number for the original bipolar version of the chip. The standard astable circuit you posted cannot achieve a true 50% duty cycle as shown. There are several versions of the same technique to achieve this, involving diodes to completely separate the charging current from the discharging current. Here are random innergoogle grabs as examples:

enter image description here

enter image description here

There are two problems with the bipolar 555 for this application. one is that it has an asymmetrical output impedance. The other is that the high and low output voltages are not spaced identically between the voltage rails. IOW, if the part is running on 12 V, the high output voltage is not as close to 12 V as the low output voltage is to 0 V.

The CMOS 555 (National's is the LMC555) does not have the standard 555's extra-beefy output stage. What it does have is a much more symmetrical output, so you can come very close to a true 50/50 output waveform without the diodes and adjustment. It also has a much higher operating frequency range so a clean, square 100 kHz output is not a strain for it to produce.

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Use these websites to check C1, R1, R2 values for NE555 in astable mode:

https://ohmslawcalculator.com/555-astable-calculator

https://www.omnicalculator.com/physics/ne555-astable

Recommended values:

C1: 1nF (1000pF) capacitor
R1: 2.2k
R2: 5.6k

This setup gives a 58.21% duty cycle at 107.66kHz. The frequency is 107.46kHz. These components are standard. For non-standard values, R1 can be 1.4943k and R2 a 6.8k precision resistor. For better accuracy, use an MCU. NE555's capacitor timing can degrade. The duty cycle shouldn't drop below 50%. Avoid using values under 1kΩ for R1 and R2.

Calculate frequency and duty cycle:

Frequency: f = 1.44 / ((R1 + 2 * R2) * C)
Duty cycle: D = T_high / T_total
    T_high = ln(2) * R1 * R2 * C1
    T_low = ln(2) * R2 * C1
    T_total = T_high + T_low

Using the values:

C1: 1nF (1000pF or 1 * 10e-9 F) capacitor
R1: 2.2k
R2: 5.6k

f = 1.44 / ((2200 + 2 * 5600) * 1 * 10e-9) = 10746.268656716416

D calculations:

ln(2) = 0.693
C1 = 10e-9
T_high = 0.693 * (2200 + 5600) * 10e-9 = 5.4053999999999994e-05
T_low = 0.693 * 5600 * 10e-9 = 3.8808e-05
T_total = 9.286199999999999e-05
D = 0.582089552238806 or 58.208%
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