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I have learnt that on the PCB, the signal tracks must be a certain distance apart to minimize cross talk. This makes sense this we must reduce the electric and magnetic field coupling across to neighbouring conductors.

I was watching some videos in which an IC package was opened to show the silicon die inside it and the bonding wires and the pads on which they connect. The bonding wires and the pads are actually very close together, very small pitch. This made me wonder, doesn't cross talk happen within an IC on the bond wires, or the pads, or even on the die itself when switching activity is taking place?

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    \$\begingroup\$ Inside the silicon chip, crosstalk can be a serious problem. Parasitic extraction is a crucial step in the design process of a modern chip. The electromagnetic effect of the entire chip layout is calculated by simulation, then necessary modifications are made. \$\endgroup\$ Commented Aug 16, 2023 at 12:53
  • \$\begingroup\$ things are only micro meter apart there or even less, cross talk must be a big deal I assume? \$\endgroup\$
    – gyuunyuu
    Commented Aug 16, 2023 at 22:17
  • \$\begingroup\$ You're only considering the bonding wires. Crosstalk between bus lines on-chip is a big deal (often a much bigger deal!) and a nightmare to fix. Often the only way is to interdigitate the bus lines with ground lines. It minimizes the required distance between the signal lines, but it's still chewing up really expensive real estate. \$\endgroup\$
    – JBH
    Commented Aug 16, 2023 at 23:44

6 Answers 6

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Xilinx provide the same die in different package options, where the maximum speed of interfaces can depend upon the package type. This shows the effect of packaging upon the rated performance of the device.

E.g. from Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) there are tables which show variations of the maximum speeds for different packages.

Looking at examples for a -2 speed grade:

  1. For DDR3 with a FF or RF package and a HP bank the maximum data rate is 1866 Mb/s (with a HP VCCAUX_IO 2.0V supply) or 1333 Mbs (with a HP VCCAUX_IO 1.8V supply): enter image description here
  2. Whereas with a FB package with a HP bank the maximum DDR3 data rate is 1066 Mb/s: enter image description here
  3. For GTX Transceiver Performance the maximum data rate can be 10.3125 Gbs/s or 6.6 Gb/s depending upon the package type: enter image description here

Another example is the PCI express hard IP in Artix® UltraScale+™ FPGAs. The UltraScale+ FPGAs Product Tables and Product Selection Guide contains:

Device Name AU7P AU10P AU15P AU20P AU25P
PCI Express® 1x Gen3x4 1x Gen4x8(1) 1x Gen4x8(1) 1x Gen3x8 1x Gen3x8

Notes:

  1. PCIe Gen4 is available in AU10P and AU15P in the FFVB676 package. AU10P and AU15P in other packages support Gen3x8.

I.e. if the AU10P or AU15P FPGAs can be used at PCIe Gen3 or Gen4 speeds depends upon the FPGA package used.

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They are very relevant!

So first off: bonding wires have very little surface, so the capacitance between them is low; they are also relatively short, so that their mutual inductance is low.

But: at higher frequencies they become a problem. (Also because they represent a break in characteristic impedance; that's one of the reasons why you often see packages that don't depend on bond wire, such as chip-scale flip-chip packages, for very high speed applications.)

On the chip level, the fact that there's significant capacitance between nearby elements is the very basic principle on which many (actually, probably most) semiconductor chips work: the field-effect transistor (FET) only works exactly because a gate together with the drain-source junction form a capacitor.

This of course means that when designing a chip, you need to make it so that capacitive coupling only happens where you want it, and that is an important design constraint already "baked" into how the layer stackup is constructed; you still must not put e.g. large metal areas close to each other, unless you want to construct a capacitor.

In the end, everything has stray capacitance to everything – that's just how the universe is. Your job as an engineer is to suppress all the stray effects such that the effects you want become dominant and the whole system manageable. There's simple examples of that: your bicycle wheels don't have to be perfectly round (such a thing does not exist), they just need to be round enough so that pedalling makes you move significantly more forward than sideways and up and down. That's the case here, as well: all the (potentially billions!) of parts in a semiconductor device need only be isolated from each other well enough that the intended currents are large enough compared to the unintended ones so that, even under thermal noise, the device still works reliably.

Of course, that means that if you need to design a high-performance chip, you'll work close to these reliability limits – for example, you make gate capacitances as small as possible (to reduce the time it takes to switch a MOSFET by charging or discharging the gate). But of course, that means that smaller stray capacitances could start to significantly change the state of the MOSFET, if a high-frequency current was applied across them.

That is exactly what the so-called Rowhammer vulnerability in modern computer memory is based on: A module of computer memory (RAM) consists of billions of MOSFETs, whose gate charge defines whether they're set to a logical "1" or a "0". Not only speed, but also size, require that these MOSFETs have very small gates and are very tightly and regularly packed. As fantastically reliable as modern RAM is, if you write software that just toggles the same bits very rapidly, you might find that surrounding MOSFET gates get charged as well, due to crosstalk between different MOSFETs and their connections.

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It certainly happens. Here is a dual opamp and the crosstalk between the two is listed:

enter image description here

Not all of the crosstalk comes from bond wires but also straight across the silicon, silicon-plastic-silicon and similar. The crosstalk value is the lumped sum of all.

As you specify switching, any digital or PWM generation IC you just need to make sure its susceptibility is low enough to not cause problems. I don’t have enough ASIC design knowledge to tell for sure, but leading edge blanking is a thing you can use if you need to literally cover some potential glitch.

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Crosstalk definitely happens.

For devices that input and output multiple channels of analog signals, e.g., analog switches or opamps, the datasheets often specify crosstalk attenuation.

In digital devices, crosstalk can become noticeable, especially when you switch many outputs at once. For example, this is from TI's LVC Characterization Information:

LVC simultaneous switching noise

However, these spikes are not outside the specified tolerances (VOH, VOL), so they do not actually matter.

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  • \$\begingroup\$ So is Simultaneous Switching Noise because of cross talk within the IC? \$\endgroup\$
    – gyuunyuu
    Commented Aug 16, 2023 at 22:22
  • \$\begingroup\$ To a certain degree, but the large current spikes caused by digital switching contribute, too. (The latter can be somewhat mitigated with decoupling capacitors.) \$\endgroup\$
    – CL.
    Commented Aug 17, 2023 at 5:45
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Good observation.

The cross-talk exists, and becomes worse for higher frequencies, as the inductance becomes more important as well.

There is some literature where bondwires have been used as inductive degeneration for LNAs. However, the cross talk and inductance value predictability are poor.

This is the reason why flip-chip packages were invented (there might be more reasons, but I can think of this one). Flip chip packages have the substrate on the top and allow copper pillars to be directly soldered to the board with much shorter connections, thus minimizing inductance and cross-talk.

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  • \$\begingroup\$ I might have come across "flip chip package" but never gave it a thought before since there are so many different package types out there \$\endgroup\$
    – gyuunyuu
    Commented Aug 16, 2023 at 22:22
  • \$\begingroup\$ Flip chip - Wikipedia \$\endgroup\$
    – Sjoerd
    Commented Aug 18, 2023 at 7:49
  • \$\begingroup\$ @gyuunyuu well, package engineering is a field of its own. At my company we had a few PhDs specialized in the area. \$\endgroup\$
    – Designalog
    Commented Aug 18, 2023 at 7:59
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Cross talk does happen. This is one reason why integrated ADCs in microcontrollers are noisier than dedicated ADC ICs.

It is also the reason why high-resolution dedicated ADCs that use a serial bus may be buffered from the SPI bus with a separate transparent latch IC. That allows the ADC's serial lines to be disconnected from the bus when the bus is not being used to communicate with the ADC. This is done because even though the ADC might not be reading the serial pins, and they may in fact be high impedance, it does not stop the logic transition from other activity between other devices on the bus from appearing at the ADC pins. This transition noise feeds into the digital sections of the ADC which then crosstalks into the analog sections.

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