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I am trying to implement Square Law Device on Virtex 5 Family FPGA but before burning it to the FPGA I was trying to simulate it in the Xilinx ISE kit. I am not sure whether the code is correct or not but here is the procedure I followed:

  1. Created the schematic
  2. Generated and Instatiated the IP Cores for Binary Counter (just for simulation purpose) and Sine Wave Generator using Cordic
  3. Inserted a Verilog Test Fixture.

But I was not successful in simulating it. I am inserting the code for the Verilog Test Fixture.

// Verilog test fixture created from schematic F:\Xilinx\demod\demod\schema.sch - Wed May 01 19:16:25 2013

`timescale 1ns / 1ps

module schema_schema_sch_tb();

// Inputs
   reg clk;

// Output
   wire [35:0] outp;

// Bidirs

// Instantiate the UUT
    schema UUT (
    .outp(outp), 
    .clk(clk)
   );

// Initialize Inputs
   `ifdef auto_init
         initial begin
             clk = 0;
                 repeat(100) begin
                     #10 clk = 1;
                     #10 clk = 0;
                 end
         end         
   `endif
endmodule

Also I am copying the schematic of the project.

Schematic of the Project Where am I wrong?

Edit: The multiplier element is red just because it got selected while taking snapshot. I tried removing the instiantion of IP cores and I got some output but not the correct one. After that I replaced the always begin loop with repeat(16) begin loop, but it shows an error near repeat.

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  • \$\begingroup\$ What did you expect to see, and what did you see instead? Also, you're probably going to need to provide a reset signal to reset modules that have internal state to a known state. Does the UUT really have no inputs other than a clock? \$\endgroup\$ – Dave Tweed May 1 '13 at 14:38
  • \$\begingroup\$ @DaveTweed The UUT was instantiated when I generated a Verilog Test Fixture from the schematic. I have no clue about the RESET thing but from schematic I am sure it doesn't have any other input. \$\endgroup\$ – mozart May 1 '13 at 14:47
  • \$\begingroup\$ why are the components internal to the UUT also instantiated in the testbench? surely you would just instantiate the uut? \$\endgroup\$ – stanri May 1 '13 at 15:07
  • \$\begingroup\$ @StaceyAnne does that mean I don't have instantiate the multiplier, counter and sine_wave? \$\endgroup\$ – mozart May 1 '13 at 15:09
  • \$\begingroup\$ @StaceyAnne I removed the other instantiating code but the output is not the one I want. Because of which I changed the code a little. Instead of running the loop forever I tried repeat loop, but it shows an error? \$\endgroup\$ – mozart May 1 '13 at 15:21
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Your initial begin block does not have an end, so you're getting a syntax error.

If you see errors past this, then please put the full text of the error into your question.

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  • \$\begingroup\$ I'm still getting the error. The error is: ERROR:HDLCompiler:806 - "F:/Xilinx/demod/demod/test_module.v" Line 30: Syntax error near "repeat". \$\endgroup\$ – mozart May 1 '13 at 16:25
  • \$\begingroup\$ The code in your post does not show that you've fixed this error. If you have an error message you need to post that with the exact code that's given you the error. \$\endgroup\$ – Tim May 1 '13 at 16:57
  • \$\begingroup\$ its the exact code that's giving me the error. \$\endgroup\$ – mozart May 1 '13 at 17:14
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    \$\begingroup\$ @mozart, the repeat block needs to be inside the initial block. initial begin clk=0; repeat(16) begin #10 clk=1; #10 clk=0; end /*for repeat*/ end /*for initial*/ \$\endgroup\$ – Greg May 1 '13 at 17:20
  • \$\begingroup\$ @Greg now the clk is shown undefined (red signal). Logically your syntax is correct according to the online sources. Thanks for help but what to do now? \$\endgroup\$ – mozart May 2 '13 at 2:44
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With The code in the current state, unless you have another file for compiler option on that defines auto_init, then the repeat block will be ignored by the compiler. If you want clk to be initialized to 0 in some conditions and X and others, then your initial block should look like this.

// Initialize Inputs
initial begin
  `ifdef auto_init
    clk = 0; // clk is 0 if auto_init is defined, otherwise default(i.e. X)
  `endif
  /* repeat block is outside the ifdef and still inside the initial block. 
   * Will run regardless of the ifdef result */
  repeat(100) begin
    #10 clk = 1;
    #10 clk = 0;
  end
end

If you want clk to initialize to 0, then the compile must read in `define auto_init before it sees `ifdef auto_init. Alternatively, you should be able to define auto_init from your compiler command line option. You will need to refer to your user manual as it is can be different between venders.

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