Miller's voltage from \$I_{ds}\$ vs \$V_{ds}\$ characteristics for different values of gate-source voltages. Miller's voltage or Miller plateau is the critical gate-source voltage at which MOSFET enters saturation region. In a typical MOSFET datasheet it is observed that there is a curve of gate-source voltage \$(V_{gs})\$ vs gate charge \$(Q_{g})\$ at different values of drain-source voltage \$(V_{ds})\$. Which curve is more relevant to find Miller voltage between on-region characteristics and the previously mentioned graph?

  • 4
    \$\begingroup\$ Can you clarify what you mean by Miller voltage? Do you mean the Early voltage? (en.wikipedia.org/wiki/Early_effect) \$\endgroup\$
    – Halleff
    Aug 19, 2023 at 5:54
  • 2
    \$\begingroup\$ Miller voltage is the critical gate-source voltage at which MOSFET enters into saturation region from linear/ohmic/triode region. \$\endgroup\$ Aug 22, 2023 at 7:12
  • 1
    \$\begingroup\$ @ArindamMaulik typically, there is already a substantial Vds before there is a Vgs. When that is the case, the MOSFET enters saturation immediately after leaving cutoff. It would only enter ohmic region if/when Vgs becomes high enough. \$\endgroup\$ Aug 26, 2023 at 11:47

3 Answers 3


Miller's voltage or Miller plateau is the critical gate-source voltage at which MOSFET enters saturation region.

A horizontal Miller plateau occurs in a MOSFET circuit with low gate current when the drain current \$I_D\$ of the MOSFET is held constant (or nearly so) by the external circuit, and the MOSFET is operating in the saturated region.

[More generally, a not necessarily horizontal feature, which might or might not be considered a "plateau", will occur in a MOSFET circuit when the \$V_{DS}\$ of the MOSFET changes while the MOSFET is operating in the saturated region.]

Explanation and justification to come.

Here are the \$I_D - V_{DS}\$ characteristics given by CircuitLab's model of the IRF530. The IRF530 obviously operates with \$V_{DS}\$ well above 12V. However, to keep the plots in nice proportions, I have limited the graph to 12V.

enter image description here

Let's place the MOSFET into a circuit with the following constraints.

  • if \$I_D \le 4 A\$ then \$V_{DS} = 8 V\$
  • if \$V_{DS}\le 8 V\$ then \$I_D = 4 A\$

We will abbreviate constraints like this as CCCV for constant-current constant-voltage.

enter image description here

When the MOSFET is placed in such a circuit with CCCV constraints imposed on the drain, then any \$(V_{DS}, I_D)\$ operating point will lie on one of the two black lines at 8V and 4A in the following diagram.

enter image description here

It is important to note that, in the case under consideration,

  • Any \$(V_{DS}, I_D)\$ operating point will lie on one of the two black lines at 8V and 4A in the above diagram diagram no matter how much or how little charge is present in the MOSFET gate!

  • Any \$(V_{DS}, I_D)\$ operating point will lie on one of the two black lines at 8V and 4A in the above diagram diagram no matter what the internal capacitances are within the MOSFET or how they may be changing

Now lets consider what happens when we add circuitry that changes the charge in the gate. In this example, we are only applying 1mA current to the gate. This might be 3 orders of magnitude smaller than what one might see in practice. We use such a small current because it makes voltage drops across parasitic impedances negligible.


We show \$V_{DS}\$, \$I_D\$, and \$V_{GS}\$, and we annotate 5 particular points of interest.

enter image description here enter image description here

In the above plot, we see the Miller plateau between the point labeled "Maximum \$I_D\$, maximum \$V_{DS}\$, and the point labeled "Boundary between saturation region and Ohmic region".

We map each point of interest onto the plot of characteristic curves overlaid with our \$V_{DS}-I_D\$ operating constraints.

enter image description here

In this graph, the segment of the horizontal black line between the point labeled "Maximum \$I_D\$, maximum \$V_{DS}\$, and the point labeled "Boundary between saturation region and Ohmic region" corresponds with operating points within the Miller plateau. Since this segment runs nearly parallel with the \$V_{GS}=5.3 V\$, the Miller plateau will occur when \$V_{GS} \approx 5.3 V\$. In fact, the Miller plateau begins slightly below \$V_{GS}=5.3 V\$, and ends at at about \$V_{GS}=5.3 V\$ almost exactly.

We have, above given the general procedure for finding the voltage of the Miller plateau in a MOSFET circuit under CCCV drain conditions, when gate current is small.

By considering how these diagrams are constructed, it should become clear that

  • The Miller plateau is flat and level when the drain is kept under a CCCV conditions, because the Miller plateau occurs in the constant current part of the operating constraints. When a MOSFET is in the saturation region and drain current is held constant, one is following, or nearly following a curve of constant \$V_{GS}\$.

  • The voltage at which the Miller plateau begins, when the drain is under CCCV constraints, is the value of \$V_{GS}\$ corresponding to the point where the constant current regime of \$I_D\$ begins. We do not need to know what the charge in the gate is, or the value of the MOSFET's internal capacitance

And to reiterate one more time

  • When a MOSFET is operated such that its drain is under a CCCV regime, any \$(V_{DS}, I_D)\$ operating point for the MOSFET will lie on either the constant voltage line or the constant current line, no matter how much or how little charge is present in the MOSFET gate! and no matter what are the internal capacitances with the MOSFET and how they are changing.

In practice, manufacturers often test gate charge characteristics with a circuit like this one taken from the datasheet of the IRFZ44N. Here the top MOSFET serves as an adjustable current limiter. This circuit approximates a CCCV regime on the drain.

enter image description here

Resistive Load Line

If a resistive load is connected between the drain and \$V_{DD}\$, the operating points of the MOSFET (under low gate current) will take a different form. The following diagram shows the operating points of a MOSFET circuit with low gate current, under a resistive load line regime.

enter image description here

We don't have as many points of interest in this graph as we did in the case of CCCV. There is no "Maximum \$I_D\$, maximum \$V_{DS}\$" point. We anticipate that as the MOSFET operating point goes from the "\$V_{GS} = V_{th}\$" point to the "Boundary between saturation and Ohmic regions" point, there will be a "feature" that might be called a plateau, but it will not be horizontal. Rather, \$V_{GS}\$ will rise from \$V_{th}\$ (i.e. 4.0 V) to somewhere in the vicinity of 5.2 V. We anticipate 5.2 V, because the "Boundary between saturation and Ohmic regions" point lies between the \$V_{GS} = 5.1 V\$ curve and the \$V_{GS} = 5.3 V\$ curve.

We now show the simulation.


enter image description here enter image description here

As anticipated, we do see a feature that might be called a plateau from \$V_{GS}=4 V\$ to \$V_{GS}=5.2 V\$.

If we made the load resistor much larger, the angle of the load line would become more horizontal, and the Miller plateau would become much more horizontal and distinct. Recalling that we used a low voltage to make our graphs have nice proportions, we are going to switch our \$V_{dd}\$ to 80V now, and run our simulation with the load resistor at 8 and at 80 \$\Omega\$ to show the effects of the load resistance on the slope of the Miller plateau.


enter image description here

Indeed, we see that with a larger resistance, the Miller plateau is much more of a plateau.

Effect of high \$I_G\$ on Miller plateau

So far, we have used low values of gate current in our investigations of Miller plateaux. Low currents are often used to test gate-charge vs gate-voltage characteristics. But in practice, gate currents are often in the ampere range, rather than the milli-ampere range. How does that affect Miller plateaux?

One obvious effect is that high gate currents will cause not insignificant voltage drops across the internal resistances of the MOSFET. In the interest of brevity, I will not illustrate examples.

Another, perhaps less obvious effect is related to the drain-source capacitance. Simulations show that the ratio between gate current and drain-source capacitance can have a substantial effect on the symmetry (or asymmetry) of the turn-on Miller plateau and the turn-off Miller plateau. Again, in the interest of brevity, I will not illustrate examples.

Which curve is more relevant to find Miller voltage between on-region characteristics and the previously mentioned graph?

So far, we have used the \$V_{DS}\$ vs \$I_D\$ characteristic curves to investigate the Miller plateau. Often these characteristic curves are not available. In the particular case where drain current is held to a CCCV regime, the full \$V_{DS}\$ vs \$I_D\$ characteristic curves are not needed. One can use the \$V_{GS}\$ vs \$I_{D(sat)}\$ transfer characteristics curve, which carries some of the same information.

The data you want to find is the value of \$V_{GS}\$ which gives the \$I_{D(sat)}\$ which is equal to the maximum current setting of the supply.

The transfer characteristics charts often look like this one from Taiwan Semiconductor's application note AN1001

enter image description here

Or with a log scale for \$I_D\$, they may look like this one from the IRF44N datasheet

enter image description here

What's all this about MOSFET architecture, transconductance, and \$C_{GD}\$?

If the voltage(s) at which the Miller plateau (or "feature") occurs are determined by the path the MOSFET circuit takes through the \$V_{DS}\$ vs \$I_D\$ characteristics curves graph, then why do some answers to this question focus instead on MOSFET architecture, transconductance and \$C_{GD}\$?

Interest in Miller plateaux stems mainly from the impact such plateaux have on switching speed and efficiency. When a MOSFET is in cutoff, \$V_{DS}\$ may be high, but \$I_D\$ is very low, so the power dissipated in the MOSFET is low. On the other hand, when the MOSFET is fully on, \$I_D\$ may be very high, but \$V_{DS}\$ is relatively low, so the dissipated power is again relatively low. However, when \$V_{DS}\$ and \$I_D\$ are both high, dissipated power is high. The area where \$V_{DS}\$ and \$I_D\$ are both high, roughly corresponds to the saturation region. Therefore, there are incentives for a designer to move the MOSFET through this region quickly.

What determines how fast the MOSFET can traverse the saturation region? That is where \$C_{GS}\$, \$C_{GD}\$, and transconductance come into play. They determine, not the voltage of the Miller plateaux, but the width, that is, the amount of charge that needs to be transferred into (or out of) the gate in order to make the MOSFET traverse the saturation region (or at least that part of the saturation region which corresponds to the Miller plateau). It is here that MOSFET architecture becomes an important factor. Different architectures can require different amounts of charge to traverse the exact same \$V_{DS}\$ vs \$I_D\$ path.

Because of the importance of parameters like \$C_{GS}\$, \$C_{DS}\$ and transconductance for switching speed and efficiency, there is a great deal of literature about these parameters. Innovation in MOSFET design aims to give MOSFETs improved values for these parameters. Much of the educational literature, as well as Manufacturer's Application Notes, approach Miller plateaux via discussion about these parameters. So it is natural for one to follow this approach when searching for the answer that was raised by the OP:

"Is it possible to determine the Miller voltage of a MOSFET from the ON-region characteristics?"

Unfortunately, looking at \$C_{GS}\$, \$C_{GD}\$ and transconductance in an attempt to solve the voltage question, is using the wrong tool for the job, and just leads down a rabbit hole.


Consider these plots from a typical MOSFET:

Gate charge and transfer characteristics

From: Nell Semi IRF260

Gate charge is measured with fixed drain current (constant current source), therefore drain voltage swing (during which Miller effect is relevant) occurs at a constant point in the transfer function (until the conditions of that function are violated, that is).

This also means the plateau is flat, as the load line follows the flat (active region) region of the drain curves.

Some manufacturers use a resistive load, which gives a sloped plateau; this doesn't make a whole lot of difference usually, because the bulk of the plateau occurs at low voltages, where Crss is highest. Example:

STP19NM50N turn-on waveform

Source: own website, https://www.seventransistorlabs.com/Images/STP19NM50N%201.045mA%20Gate%20Charge%20400V%2030.1%20ohm%20Drain.png

Waveforms are IG (Ch2, ~1mA/div), VGS (Ch3, 10x) and VDS (Ch1, 10x), in common-source configuration. Notice for this 500V type, Vds drops rapidly after very little charge, because Crss is so tiny at high VDS. The rest of the plateau is at low VDS so the voltage drop across the resistor, and therefore ID, changes little. The exact way VDS changes during the plateau, varies between MOSFET types.

Apparent plateau can be higher or lower due to source inductance × \$\frac{dI}{dt}\$ as well, often both during a cycle; in that case the mean plateau voltage is determined by drain current. Though in a real application, turn-on and turn-off currents will differ, and so will the voltages further. Characterizing the system allows these effects to be separated and measured.

The plateau might also never appear, in cases where the assumptions for Miller effect do not apply. In switching converters, this is typically ZVS switching, where VDS remains zero while VGS is rising/falling. Note the above test was done with quite "weak" gate drive (1mA), so that drain voltage changes slowly, ensuring Miller effect shows up.

If the load current is small (relative to Coss and tf), strong gate drive will violate this assumption; note that QDG is still drawn from the gate, but at a delay (when VDS is changing, which thus happens later past the falling edge of VGS), where it doesn't look much like Miller effect anymore.

Put another way, ZVS or other dynamic conditions no longer follow a constant-current load line, thus violating the assumption that the transistor has constant current flow, or passes through a linear amplifying region at all.


What application notes and datasheets mean when writing about gate plateau (Miller plateau) voltage is a relatively constant region of Vgp(Id) due to the high transconductance of power VDMOS MOSFETs. This phenomenon occurs in the vicinity of abrupt change in Cgd(Vgd).

The VDMOS layout is entirely different from the textbook pictures of lateral MOSFET: its source and drain are on opposite sides of die. This results in a characteristic behavior of VDMOS nonlinear gate-drain capacitance

leftV = -10
rightV = 10
v = np.linspace(leftV,rightV,2000, endpoint= False)
Cgd = np.where(v<0, 
                 (Cgdmin/(np.pi/2)+Cgdmax)/(1+np.pi/2)-Cgdmin/(np.pi/2)) * np.arctan(A*v) + s, 
                 (Cgdmax-(Cgdmin+(np.pi/2)*Cgdmax)/(1+np.pi/2)) * np.tanh(A*v) + s


You can examine the BSP89 behavior in the simulation where the BSP89 model is dissected and the parasitic resistances and capacitances are moved into the circuit.

Cgd is low in cutoff and there is a significant contribution of the channel when in inversion. Unlike VDMOS, in lateral MOSFETS the channel contributes to Cgd only in weak inversion; in strong inversion only the drain overlap term contributes, as is also the case in cutoff.

This abrupt change in Cgd behavior, in the vicinity of zero Vgd value, is the only reason of the gate plateau (Miller plateau) existence. Notice that the plateau regions appear when the Vgd( =V(D_int)-V(G_int) ) graph reaches zero. The gate voltage Vgs( =V(G_int)-V(S_int) ) is almost constant while Vgd is small.


The original BSP89 SPICE model (from LTspice's standard.mos library) reads in the comment text (in blue); the "dissected" model is in the .model directive. I reproduce the model gate-drain capacitance behavior with the non-linear variable capacitor Cgd. The capacitor's charge parameter Q=s*(-x*atan(A*x)+ln(1+(A*x)**2)/(A*2))+y*x is the integral of the model nonlinear capacitance (Cgdmin/(np.pi/2)+Cgdmax)/(1+np.pi/2)-Cgdmin/(np.pi/2))*np.arctan(A*v) + s times voltage drop. The simulation against the original BSP89 model gives the identical plot.


To delve deeper into the power MOSFET internals, one can examine the currents and voltages and compare how the drain current is shared among the channel versus the parasitics.

Notice also that, in the Miller plateau phenomenon, the VDMOS specifics reveal itself only through a special Cgd behavior of trench MOSFETs. The plateau regions in transients can be reproduced with a monolithic NMOS transistor augmented with an external nonlinear drain-to-gate capacitor:


Notice that with an unreal great transconductance in simulation, Kp=100, the Miller plateau voltage becomes equal to the threshold voltage:


In this aspect, the OP suspicion about possible connection between Miller plateau and threshold voltages comes true.

Following the discussion, here is the simulation run with the BSP89 model from the manufacturer (Infineon) website; Infineon's spice model of BSP89 exposed as a circuit in a dashed rectangle:


  • \$\begingroup\$ 1) "due to the high transconductance of power VDMOS MOSFETs." Miller plateaux are present in ALL MOSFET circuits with a voltage limited constant current drain regime. Miller plateaux and not peculiar to VDMOS. 2) Miller plateau at threshold voltage is characteristic of drain connected to V_DD through resistor. \$\endgroup\$ Aug 29, 2023 at 11:52
  • \$\begingroup\$ This is a topic beside what OP asked for, but is an interesting one by itself: in fact, the situation is even weirder as Cgd is not a function of Vgd, but Vds! (Or both in general, but Vds is dominant.) I had made measurements of this, but I don't think I have any data handy anymore. Do not take the SPICE model as gospel: they made the same (reasonable, but faulty!) assumption. Measure the real device! \$\endgroup\$ Aug 30, 2023 at 1:59
  • \$\begingroup\$ "I'm from Jamaica, the "Show Me" island. So show me you're blowing it out your fanny." ( (C) Futurama, The Sting episode ). Seriously, show the visitors to this page that Miller plateaux are present in ALL MOSFET circuits with a voltage limited constant current drain regime as the serious problem for system designers, and not just some negligible notches in transients. Please, do not just confidently proclaim your opinion, but try and justify this and the other claims of yours. If you can spare your leisure time \$\endgroup\$
    – V.V.T
    Aug 30, 2023 at 5:41
  • \$\begingroup\$ @Tim Williams: you're right, I used the post as an opportunity in hope to attract attention to SPICE models of power MOSFET in LTspice, the simulator much popular with electronics.SE posters and experts. The attempt has failed to get noticed: for example, nobody seems to care that Cgd=f(Vgd) has two branches like in if(Vgd<0){Cgd=k1*arctan(A*v)+s}else{Cgd=k2*tanh(A*v)+s}) while the BSP89 model (not just my decriptage, but also standard.mos's original model) seems to use a nonconditional expression with only arctan part. \$\endgroup\$
    – V.V.T
    Aug 30, 2023 at 5:46
  • \$\begingroup\$ And you are twice right that the SPICE models are not gospel. However, we need to develop the models to be as perfect as we can get, since the simulation is an unavoidable stage of any serious design effort. \$\endgroup\$
    – V.V.T
    Aug 30, 2023 at 5:47

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